Effect of body-to-source bias on the analog characteristics of 0.35 μm partially depleted SOI CMOS for low-voltage low-power mixed-mode applications

Babcock, J.A.; Francis, P.; Haggag, H.; Darmawan, J.; Lee, T.-W.; Lindorfer, P.; Olgaard, C.; Merrill, R.B.; Schroder, D. K.

doi:10.1109/soi.1998.723093

Cited by 5 publications

(3 citation statements)

References 6 publications

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“…The application of a positive substrate bias in a nMOSFET has many advantages in analog and digital circuits. For example, in analog applications, better transistor matching and enhanced low-power analog performance can be achieved by applying a forward substrate bias [11]. Lower flicker noise is also obtained in such bias condition [12].…”

Section: Introductionmentioning

confidence: 99%

Auger recombination-enhanced hot carrier degradation in nMOSFETs with a forward substrate bias

Tsai

Chen

et al. 2003

IEEE Trans. Electron Devices

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Enhanced hot carrier degradation in nMOSFETs with a forward substrate bias is observed. The degradation cannot be explained by conventional channel hot electron effects. Instead, an Auger recombination-assisted hot electron process is proposed. In the process, holes are injected from the forwardbiased substrate and provide for Auger recombination with electrons in the channel, thus substantially increasing channel hot electron energy. Measured hot electron gate current and the light emission spectrum provide evidence that the high-energy tail of channel electrons is increased with a positive substrate bias. The drain current degradation is about ten times more serious in forward-biased substrate mode than in standard mode. The Auger-enhanced degradation exhibits positive temperature dependence and may appear to be a severe reliability issue in high temperature operation condition.

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Section: Introductionmentioning

confidence: 99%

Auger recombination-enhanced hot carrier degradation in nMOSFETs with a forward substrate bias

Tsai

Chen

et al. 2003

IEEE Trans. Electron Devices

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“…However, it is shown in this section that, besides the aforementioned benefits, FBB improves the intrinsic device characteristics by mitigating short channel effects [21], [22]. In short channel devices, the gate is not the only terminal that has control over the channelthe drain also controls the channel through the size of the depletion region it creates.…”

Section: B Mitigation Of Output Conductance Degradation Due To Shortmentioning

confidence: 98%

Short Channel Output Conductance Enhancement Through Forward Body Biasing to Realize a 0.5 V 250 0.6–4.2 GHz Current-Reuse CMOS LNA

Parvizi

Allidina²,

El-Gamal

2016

IEEE J. Solid-State Circuits

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This work examines the use of a forward body biasing (FBB) scheme to mitigate output conductance degradation due to short channel effects in ultra-low voltage (ULV) circuits with no additional power consumption. It is shown that FBB boosts the output resistance of a transistor such that the intrinsic gain reduction due to low-supply voltages can be compensated. This technique is then used to implement a low-noise amplifier (LNA) tailored for ultra-low power (ULP) and ULV applications. The proposed LNA uses common-gate (CG) NMOS transistors as input devices in a complementary current-reuse structure. Low-power input matching is achieved by employing an active shunt-feedback architecture while the current of the feedback stage is also reused by the input transistor. Moreover, a separate FBB scheme is exploited to tune the feedback coefficient. An inductive g m-boosting technique is used to increase the bandwidth of the LNA without additional power consumption. The proposed LNA is implemented in an IBM 0.13 µm 1P8M CMOS technology and occupies 0.39 mm 2 . The measured LNA has a 14 dB gain, 4 dB minimum noise figure, IIP3 of −10 dBm, and 0.6-4.2 GHz bandwidth, while consuming only 500 µA from a 0.5 V supply. The LNA operates with supplies as low as 0.4 V while maintaining good performance. Index Terms-Current-reuse, forward body bias (FBB),inductive gm-boosting, low-noise amplifier (LNA), short channel effect mitigation, tunable active shunt-feedback, ultra-low power (ULP), ultra-low voltage (ULV). His research interests include ultra-low power IC design, MEMS-based microsystems, advanced packaging, and efficient high-volume test and calibration strategies. Mourad N. El-Gamal (S'92-M'99) received the B.Sc. (Hons.) degree from Ain-Shams University, Cairo, Egypt, in 1987, the M.Sc. degree (minor in computer science) from Vanderbilt University,

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“…• The [90,82,83]speed in bulk devices is much determined by the relative magnitude of the parasitic drain and source junction capacitances compared with the gate capacitance, which is increasing as the devices are scaled down and doping levels are increased.…”

Section: Soi Advantagesmentioning

confidence: 99%

Silicon on Insulator Technology Review

Singh¹,

Saxena²,

Rastogi³

2011

IJESET

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Effect of body-to-source bias on the analog characteristics of 0.35 μm partially depleted SOI CMOS for low-voltage low-power mixed-mode applications

Cited by 5 publications

References 6 publications

Auger recombination-enhanced hot carrier degradation in nMOSFETs with a forward substrate bias

Auger recombination-enhanced hot carrier degradation in nMOSFETs with a forward substrate bias

Short Channel Output Conductance Enhancement Through Forward Body Biasing to Realize a 0.5 V 250 0.6–4.2 GHz Current-Reuse CMOS LNA

Silicon on Insulator Technology Review

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