Effect of surface roughness of trench sidewalls on electrical properties in 4H-SiC trench MOSFETs

Abstract

The effects of the surface roughness of trench sidewalls on electrical properties have been investigated in 4H-SiC trench MOSFETs. The surface roughness of trench sidewalls was well controlled and evaluated by atomic force microscopy. The effective channel mobility at each measurement temperature was analyzed on the basis of the mobility model including optical phonon scattering. The results revealed that surface roughness scattering had a small contribution to channel mobility, and at the arithmetic average roughness in the range of 0.4-1.4 nm, there was no correlation between the experimental surface roughness and the surface roughness scattering mobility. On the other hand, the characteristics of the gate leakage current and constant current stress time-dependent dielectric breakdown tests demonstrated that surface morphology had great impact on the long-term reliability of gate oxides.

X-ray imaging and spectroscopy of nitrogen in the SiO2/SiC interface of the 4H–SiC MOSFET trench sidewalls

“…Given this, the atomic steps would be much closer to the atomic order if the sidewall was flat. As reported by Kutsuki et al 19) the surface of SiC was rough due to the use of a dry etching technique for the formation of the trench; this, in turn, caused an increase in the atomic steps. Thus, the site of the introduced nitrogen and the atomic structure around the nitrogen atoms were assumed to be different for the trench sidewall and the planar SiC due to the influence of the atomic steps and the surface roughness.…”

“…However, the trench's sidewall has been shown to contain slopes and irregularities that are in contrast to the structure of the planar m-face SiC wafers. 19) The presence of these irregularities has implications for the location of the nitrogen atom as it is highly unlikely that the introduction of the nitrogen atom occurs at the same site as that seen in the planar SiC wafer. Since this can affect the device's electrical properties, direct measurements using a SiC trench sidewall that has a channel region in which the current is controlled is necessary.…”

“…The wafer was cleaved along the trench (as shown by the dotted red line in Fig. 1), and the SiO 2 film was removed via the wet etching technique in which aqueous hydrogen fluoride (HF) was used to expose the trench sidewall, as reported by Kutsuki et al 19) Complete removal of the SiO 2 film was not done as there was still a layer of film at the bottom of the trench. Figure 1 shows the SEM of the trench sidewall on the SiC side (m-face) of the SiO 2 /SiC interface.…”

Enhancement of channel mobility in 4H-SiC trench MOSFET by inducing stress at SiO2/SiC gate interface

“…In SiC-MOSFETs, μ eff can be divided into three components based on the scattering factors, namely the Coulomb scattering mobility (μ C ), optical phonon scattering mobility (μ opt ), and surface roughness scattering mobility (μ SR ). [29][30][31] These scattering mobility values were calculated from the temperature dependence of μ eff versus the effective field (E eff ). 23) 3.…”

Comparison of Commercial Planar and Trench SiC MOSFETs by Electrical Characterization of Performance-Degrading Near-Interface Traps

“…Kutsuki et al fabricated one-cell trench SiC MOSFET and suggested that optical phonon scattering, derived from lattice vibrations, must be considered with acoustic phonon scattering in conventional scattering models [13]. Compared to surface roughness scattering, Coulomb scattering and optical phonon scattering had a greater impact on channel-carrier mobility [14], [15]. Since the evaluation of the trench sidewalls and their impact on the channel carriers is complex, there is no coherent scattering mechanism that can explain the channel mobility in trench MOSFETs [16].…”