Effects of Device Structure and Back Biasing on HCI and NBTI in Silicon-on-Thin-BOX (SOTB) CMOSFET

Ishigaki, Takashi; Tsuchiya, R.; Morita, Yusuke; Sugii, Nobuyuki; Kimura, S.

doi:10.1109/ted.2011.2107520

Cited by 24 publications

(11 citation statements)

References 18 publications

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“…4 Hot-carrier lifetimes are commonly predicted using stressing devices at high drain voltages, setting the gate voltage to correspond to the maximum substrate current (I B ), and measuring the degradation of the device over time. 5 In conventional long-channel MOSFETs, the strongest degradation is reported at V G ¼ V D /2, and the worst HCS in short-channel devices is reported at V G ¼ V D. 6 However, differences in reliability between FinFETs and conventional MOSFETs have not been quantified, and the characteristics of HCS-induced FinFET degradation remain unclear.…”

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confidence: 99%

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Examination of hot-carrier stress induced degradation on fin field-effect transistor

et al. 2014

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Articles you may be interested inPhysical understanding of different drain-induced-barrier-lowering variations in high-k/metal gate n-channel metal-oxide-semiconductor-field-effect-transistors induced by charge trapping under normal and reverse channel hot carrier stresses Abnormal threshold voltage shift under hot carrier stress in Ti1−xNx/HfO2 p-channel metal-oxide-semiconductor field-effect transistors Hot carrier effect on gate-induced drain leakage current in high-k/metal gate n-channel metal-oxidesemiconductor field-effect transistors Appl. Phys. Lett. 99, 012106 (2011); 10.1063/1.3608241Convergence of hot-carrier-induced saturation-region drain current and linear-region drain current degradation in advanced n-channel metal-oxide-semiconductor field-effect transistors

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confidence: 99%

“…[8][9][10] Conversely, when the value of n was approximately 0.2-0.3, 7 damage was caused by the injection of hot electrons into the oxide, and oxide traps formed in response to device degradation. [5][6][7] The combination of trapped charge and interface states was also reported, 11 and the power-law time exponent was believed to lie between 0.3 and 0.5.…”

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confidence: 99%

Examination of hot-carrier stress induced degradation on fin field-effect transistor

et al. 2014

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“…The 65-nm Silicon-On-Thin-BOX (SOTB) process was chosen due to its low-power feature [27]. Furthermore, it can provide the chip with the back-gate biasing technique, which allows us to enhance the chip performances further [28]. The chip layout sits on a die area of 1.32-mm 2 , which equivalents to 349,061 of NAND2 gate-counts.…”

Section: Risc-v Is An Open-source Isa That Was First Presented By Thementioning

confidence: 99%

Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB)

Hoang

Duran

Nguyen

et al. 2020

IEICE Electron. Express

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In this paper, a 32-bit RISC-V microcontroller in a 65-nm Silicon-On-Thin-BOX (SOTB) chip is presented. The system is developed based on the VexRiscv Central Processing Unit (CPU) with the Instruction Set Architecture (ISA) extensions of RV32IM. Besides the core processor, the System-on-Chip (SoC) contains 8KB of boot ROM, 64KB of on-chip memory, UART controller, SPI controller, timer, and GPIOs for LEDs and switches. The 8KB of boot ROM has 7KB of hard-code in combinational logics and 1KB of a stack in SRAM. The proposed SoC performs the Dhrystone and Coremark benchmarks with the results of 1.27 DMIPS/MHz and 2.4 Coremark/MHz, respectively. The layout occupies 1.32-mm 2 of die area, which equivalents to 349,061 of NAND2 gate-counts. The 65-nm SOTB process is chosen not only because of its low-power feature but also because of the back-gate biasing technique that allows us to control the microcontroller to favor the low-power or the high-performance operations. The measurement results show that the highest operating frequency of 156-MHz is achieved at 1.2-V supply voltage (V DD) with +1.6-V back-gate bias voltage (V BB). The best power density of 33.4-W/MHz is reached at 0.5-V V DD with +0.8-V V BB. The least current leakage of 3-nA is retrieved at 0.5-V V DD with −2.0-V V BB .

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“…SOTB is a type of fully depleted SOI (FD-SOI) process. [26][27][28][29][30] It reduces variations due to impurities because it does not add any dopant to a channel of MOSFETs. A special feature of SOTB is that the BOX layer is less than 10 nm.…”

Section: Degradation Caused By Plasma-induced Damagementioning

confidence: 99%

Initial and long-term frequency degradation of ring oscillators caused by plasma-induced damage in 65 nm bulk and fully depleted silicon-on-insulator processes

Kishida¹,

Oshima

Yabuuchi

et al. 2015

Jpn. J. Appl. Phys.

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The degradation of reliability caused by plasma-induced damage (PID) has become a significant concern with the miniaturization of device size. In particular, it is difficult to relieve PID in silicon-on-insulator (SOI) because it contains buried oxide (BOX) layers. In this work, we compare PID between a bulk and a silicon on thin BOX (SOTB), which has BOX layers of less than 10 nm. We measure frequencies of ring oscillators with an antenna structure on a single stage. In the bulk, PID is relieved by first connecting an antenna to a drain because electric charge flows to a substrate. The difference in initial frequency is 0.79% between structures, which cause and relieve PID. SOTB also relieves the same amount of PID. Initial frequencies are affected by PID, but there is no effect of PID on the long-term degradation mainly caused by bias temperature instability (BTI).

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Effects of Device Structure and Back Biasing on HCI and NBTI in Silicon-on-Thin-BOX (SOTB) CMOSFET

Cited by 24 publications

References 18 publications

Examination of hot-carrier stress induced degradation on fin field-effect transistor

Examination of hot-carrier stress induced degradation on fin field-effect transistor

Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB)

Initial and long-term frequency degradation of ring oscillators caused by plasma-induced damage in 65 nm bulk and fully depleted silicon-on-insulator processes

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