Effects of low temperature annealing on the ultrathin La2O3 gate dielectric; comparison of post deposition annealing and post metallization annealing

Ng, Jin Aun; Kuroki, Yusuke; Sugii, Nobuyuki; Kakushima, Kuniyuki; Ohmi, S.; Tsutsui, Kazuo; Hattori, Takeo; Iwai, Hiroshi; Wong, Hei

doi:10.1016/j.mee.2005.04.019

Cited by 42 publications

(26 citation statements)

References 7 publications

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“…Peak mobilities of 312 cm 2 /Vs and 244 cm 2 /Vs were obtained from the samples annealed at 300 • C in N 2 and O 2 ambients, respectively. The peak mobility of 312 cm 2 /Vs that we obtained is higher than the previous reported values [7,8]. The leakage current density is 6.8 × 10 −6 A/cm 2 at EOT = 1.7 nm (PDA at 300 • C in N 2 ambient for 10 minutes), which is 10 −3 A/cm 2 lower than the published values for HfSiON [12].…”

Section: Methodscontrasting

confidence: 81%

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Effective mobility and interface-state density of La2O3 nMISFETs after post deposition annealing

Ng¹,

Sugii

Kakushima

et al. 2006

IEICE Electron. Express

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Abstract:In this paper, we reported the effective mobility and the interface-state density of La 2 O 3 nMISFETs fabricated under different post deposition annealing (PDA) conditions; annealing temperature (300 • C -600 • C) and ambient (N 2 or O 2 ). High effective mobility of 312 cm 2 /Vs and low interface-state density of 6 × 10 10 cm −2 /eV were obtained from La 2 O 3 nMISFET with equivalent oxide thickness (EOT) of 1.7 nm after PDA at 300 • C in N 2 ambient for 10 minutes. Gate leakage current density was 6.8 × 10 −6 A/cm 2 . We found that peak effective mobility decreased with increasing anneal temperature, regardless of annealing ambient. We also observed a monotonous relationship between effective mobility and interface-state density. This behavior suggests that lowering the interface-state density is essential to obtain high mobility in the high-κ/Si structure. and Al 2 O 3 gate dielectrics with equivalent oxide thickness 5-10Å," Symp.

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Section: Methodscontrasting

confidence: 81%

“…According to the ITRS, lanthanum oxide (La 2 O 3 ), which is a member of rare earth oxide (REO), was classified into the next group of potential candidates to succeed Hf-based oxides [2]. Thus, La 2 O 3 has attracted much attention in recent years and detailed analyses were reported [3,4,5,6,7,8,9].…”

Section: Introductionmentioning

confidence: 99%

Effective mobility and interface-state density of La2O3 nMISFETs after post deposition annealing

Ng¹,

Sugii

Kakushima

et al. 2006

IEICE Electron. Express

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“…Agilent 4284A multi-frequency LCR meter, Agilent 4156C semiconductor parameter analyzer and Agilent 41501B SMU and pulse-generator expander were used for the electrical characteristics measurements. [9]. Furthermore, the La 2 O 3 /SiO 2 gate stack nMOSFET should gives roughly the same subthreshold slope property as the SiO 2 reference sample (66 mV/dec.).…”

Section: Methodsmentioning

confidence: 84%

Mobility Degradation Analysis for La2O3 nMOSFET

Luna-Sánchez

González-Martínez

2006

ECS Trans.

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nMOSFET with various thicknesses of the La 2 O 3 layer and the SiO 2 interfacial layer (IL) were fabricated. We discussed mobility degradation caused by fixed charge and trapped charge at the La 2 O 3 /SiO 2 interface. IntroductionThe ultrathin gate dielectric has emerged as one of the most difficult challenges for future device scaling. According to the International Technology Roadmap of Semiconductors 2005 (ITRS2005), progress in scaling silicon oxynitride dielectric layer below 1 nm thickness (in equivalent oxide thickness, EOT) is considered impracticable because of high leakage current [1]. High dielectric constant materials (high-κ) is needed as early as in year 2008 for the 57 nm 1 / 2 pitch generation [1]. For this reason, much effort is currently underway on high-κ gate dielectrics.Hf-based family of high-κ gate dielectrics has been extensively studied during the past few years and is expected to be used starting year 2008. On the other hand, Group III or rare earth oxides (REOs), especially Lanthanum oxide (La 2 O 3 ) and Y 2 O 3 , are promising candidates to replace Hf-based gate dielectrics as the future gate dielectric. Detailed analyses of La 2 O 3 on interface structure by X-ray photoelectron spectroscopy (XPS) [2-3], conduction mechanisms [4][5], annealing effects [6-7] and promising electrical characteristics of MOSFETs [8-9] were reported.However, the effective mobility of high-κ gate dielectric MOSFETs is found to be significantly lower than the universal curve [10]. Furthermore, mobility degradation mechanism is still not completely clarified. In this paper, by changing the SiO 2 interfacial layer (IL) thickness [11], we studied the effect of fixed and trapped charge at La 2 O 3 /SiO 2 interface on mobility degradation. Charge pumping technique was used to evaluate the interface trap of this system. ExperimentsUltrathin La 2 O 3 films (EOT 1.1 nm and 2 nm) were deposited on thermal SiO 2 interfacial layers (IL) (0.9-2 nm) by electron-beam evaporation in a molecular-beamepitaxy (MBE) system. The chamber pressure and temperature during the deposition were 10 -7 Pa and 250 o C, respectively. The ex-situ post deposition anneal (PDA) was ECS Transactions, 2 (1) 329-338 (2006) 10.1149/1.2193905, copyright The Electrochemical Society 329 ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 128.6.235.18 Downloaded on 2015-06-04 to IP 330conducted in the rapid thermal annealing (RTA) chamber with 1.2 l/min flow rate at 300 o C in either N 2 or O 2 ambient for 10 minutes before the Al gate electrode evaporation using bell-jar type evaporator at 10 -5 Pa. The gas lines and RTA chamber were carefully purged to minimize contamination of existing gases and particles prior to annealing. To avoid possible contamination on La 2 O 3 film and moisture absorption, the exposure time before Al gate evaporation was less than 1 hour. Gate length and width of the nMOSFET were 10 and 57 µm, respectively. Figure 1 outlines major fabrication steps...

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“…The issue of leakage current is dependent on band offset features of the lanthanum silicate, which will be calculated after identification of its crystalline structure. Considering all the above discussion summarized in Table I, it is suspected that an optimum annealing temperature for achieving the best gate properties is in the range from room temperature to 500 o C, for example, 300 o C [7]. …”

Section: Discussionmentioning

confidence: 99%

High-resolution TEM/STEM analysis of SiO<inf>2</inf>/Si(100) and La<inf>2</inf>O<inf>3</inf>/Si(100) interfaces

Tanaka

Yamasaki

Inamoto

et al. 2006

2006 International Workshop on Nano CMOS

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We have performed direct observations and elemental analyses of SiO 2 /Si(100) and La 2 O 3 /Si(100) by spherical aberration-corrected transmission electron microscopy (TEM) / scanning TEM (STEM) and "combinatorial analyses" by energy dispersive X-ray analysis (EDX) and electron energy loss spectroscopy (EELS). In SiO 2 /Si(100), the interfacial structures have been clearly observed without artificial image contrast. Atomic steps and defects on the Si(100) surfaces have been accurately identified. In La 2 O 3 /Si(100), epitaxial double layers have been observed after depositon at room temperature. These layers have been identified with lanthanum silicate and silicon oxide including a small amount of lanthanum atoms. Annealing at 500 o C for 10 min have caused growth of both of the layers and exclusion of the lanthanum atoms from the silicon oxide layer. The growth mechanism of the layered structure and its influences on gate properties in MOSFETs have been discussed based on our experimental data.

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Effects of low temperature annealing on the ultrathin La2O3 gate dielectric; comparison of post deposition annealing and post metallization annealing

Cited by 42 publications

References 7 publications

Effective mobility and interface-state density of La2O3 nMISFETs after post deposition annealing

Effective mobility and interface-state density of La2O3 nMISFETs after post deposition annealing

Mobility Degradation Analysis for La2O3 nMOSFET

High-resolution TEM/STEM analysis of SiO<inf>2</inf>/Si(100) and La<inf>2</inf>O<inf>3</inf>/Si(100) interfaces

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