Efficiency improvement of the solar PV-system using nanofluid and developed inverter topology

Mustafa, Uvais; Qeays, Ibraheem Ahmed; Arif, M. Saad Bin; Yahya, Syed Mohd; Ayob, Shahrin Md.

doi:10.1080/15567036.2020.1808119

Cited by 13 publications

(8 citation statements)

References 31 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…One of the main limitations of the proposed structure is the utilization of bi-directional switches, which adds to the device count and increases the TSV p.u. Although MLIs find application in various fields, integrating renewable resources into the utility grid is one of the most prominent applications [8]. The proposed topology based on the above discussion is suitable for solar PV applications.…”

Section: Discussion and Comparative Analysismentioning

confidence: 98%

“…Having a higher number of dc links ensures better waveforms of the output voltage and current. However, having a higher number of dc sources is a disadvantage as it increases complexity and cost to the system [8]. Capacitors can be employed to increase the dc links with a reduced number of dc sources, but this requires careful consideration.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Asymmetrical 17-Level Inverter Topology With Reduced Total Standing Voltage and Device Count

et al. 2021

Self Cite

View full text Add to dashboard Cite

Voltage source Multilevel Inverters (MLIs) are vital components for medium voltage and high-power applications due to their advantages like modularity and better power quality. However, the number of components used is significant. In this paper, an improved asymmetrical multilevel inverter topology is proposed producing 17-levels output voltage utilizing two dc sources. The circuit is developed to reduce the number of isolated dc-sources used without reducing output levels. The circuit utilizes six two-quadrant switches, three four-quadrant switches and four capacitors. The capacitors are self-balancing and do not require extra attention, i.e. the control system is simple for the proposed MLI. Detailed analysis of the topology under linear and non-linear loading conditions is carried out. Comparison with other similar topologies shows that the proposed topology is superior in device count, power quality, Total Standing Voltage (TSV), and cost factor. The performance of the topology is validated for different load conditions through MATLAB/Simulink environment and the prototype developed in the laboratory. Furthermore, thermal analysis of the circuit is done, and the losses are calculated via PLECS software. The topology offers a total harmonic distortion (THD) of 4.79% in the output voltage, with all the lower order harmonics being less than 5% complying with the IEEE standards.

show abstract

Section: Discussion and Comparative Analysismentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

Asymmetrical 17-Level Inverter Topology With Reduced Total Standing Voltage and Device Count

et al. 2021

Self Cite

View full text Add to dashboard Cite

show abstract

“…The switching losses are calculated based on energy loss. These include turn-off losses and turn-on losses and can be calculated as described in [8]:…”

Section: Power Loss Analysismentioning

confidence: 99%

“…Thus, the proposed topology is efficient and has a lower number of sources suitable for renewable energy applications. Thus, considering the comparative study above and the experimental as well as simulation analysis, following remarks regarding the problems solved by the proposed topology can be made: Although there are various applications suitable for multilevel inverters such as Electric Vehicles [36], integration of solar panels into utility grid with MLI acting as interface [8] etc, considering the discussion above it is safe to say that the proposed topology is suitable for renewable energy applications, especially solar PV-based applications. Since the proposed topology is asymmetric, one of the main disadvantages is that it requires a large variety of DC sources in cascaded structures.…”

Section: Comparison Based On Efficiencymentioning

confidence: 99%

“…The switching losses are calculated based on energy loss. These include turn‐off losses and turn‐on losses and can be calculated as described in [8]:

\begin{matrix} true \\ right E_{off, k} & = & left \int_{0}^{t_{off}} v ((), t) i ((), t) d t \\ = & left \int_{0}^{t_{off}} ([], ((), \frac{V_{sw, k}}{t_{off}} t) ((), - \frac{I}{t_{off}} ((), t - t_{off}))) d t \\ = & left \frac{1}{6} V_{sw, k} I t_{off} . \end{matrix}

Similarly,

\begin{matrix} true \\ right E_{on, k} & = & left \int_{0}^{t_{on}} v ((), t) i ((), t) d t \\ = & left \int_{0}^{t_{on}} ([], ((), \frac{V_{sw, k}}{t_{on}} t) ((), - \frac{I^{'}}{t_{on}} ((), t - t_{o n}))) d t \\ = & left \frac{1}{6} V_{sw, k} I^{'} t_{on}, \end{matrix}

…”

Section: Power Loss Analysismentioning

confidence: 99%

See 1 more Smart Citation

An improved asymmetrical multi‐level inverter topology with boosted output voltage and reduced components count

Arif

Mustafa²,

Siddique

et al. 2021

IET Power Electronics

Self Cite

View full text Add to dashboard Cite

This paper presents an improved Multi-level Inverter topology utilizing the concept of boosting-capacitor and two DC sources with reduced switches count for generating 17level output. The topology employs 10 unidirectional switches including one bidirectional switch. Comparison with other recent topologies shows that the proposed topology employs a reduced number of devices and better performance. The topology combines the modularity of H-Bridge with the boosting capacity of the switched capacitor topology. Special care is taken while designing the switching strategy for voltage balancing of the capacitors. The authors also have generalized the topology to produce 'n' level output. Relevant expressions are also formed and reported. Experimental validation, as well as simulation, is performed, and results are verified. Nearest level control is used as the modulation technique.

show abstract

Efficient optimization of parallel micro-channel heat sinks based on flow resistance network model

Zhang

et al. 2023

Applied Thermal Engineering

View full text Add to dashboard Cite

Efficiency improvement of the solar PV-system using nanofluid and developed inverter topology

Cited by 13 publications

References 31 publications

Asymmetrical 17-Level Inverter Topology With Reduced Total Standing Voltage and Device Count

Asymmetrical 17-Level Inverter Topology With Reduced Total Standing Voltage and Device Count

An improved asymmetrical multi‐level inverter topology with boosted output voltage and reduced components count

Efficient optimization of parallel micro-channel heat sinks based on flow resistance network model

Contact Info

Product

Resources

About