An improved asymmetrical multi‐level inverter topology with boosted output voltage and reduced components count

Abstract

This paper presents an improved Multi-level Inverter topology utilizing the concept of boosting-capacitor and two DC sources with reduced switches count for generating 17level output. The topology employs 10 unidirectional switches including one bidirectional switch. Comparison with other recent topologies shows that the proposed topology employs a reduced number of devices and better performance. The topology combines the modularity of H-Bridge with the boosting capacity of the switched capacitor topology. Special care is taken while designing the switching strategy for voltage balancing of the capacitors. The authors also have generalized the topology to produce 'n' level output. Relevant expressions are also formed and reported. Experimental validation, as well as simulation, is performed, and results are verified. Nearest level control is used as the modulation technique.

Design and Implementation of Asymmetrical Multilevel Inverter With Reduced Components and Low Voltage Stress

“…This represents the amount of stress distribution among the switches. It is the ratio of voltage stress over a single switch to circuit's maximum stress [27], which is calculated from equation ( 16). The voltage stress across each power switch along with the maximum stress for 33-level MLI is represented in The four switches S1, S2, S5, S6 experience a stress of 31Vdc, which is 58 % of the total stress distribution, while the remaining eight switches S3, S4, S7, S8, S9, S10, S11, S12 experience a stress of 22Vdc, which is 42 % of the total stress distribution in the proposed 33-level MLI structure.…”

“…Even though these topologies offer an output levels count with a limited sources count, they have a more switches count [26]. Each module in [27] delivers 9 level and 17 level voltage outputs in symmetric and asymmetric ways with 10 power switches and 4 input sources. Another system proposed by [28] uses 10 switches to generate seventeen levels.…”

Asymmetrical 17-Level Inverter Topology With Reduced Total Standing Voltage and Device Count

“…The inrush current mainly depends on the maximum voltage difference between the capacitor voltage and the source providing the charge and various circuit parameters involved in the charging loop. The peak value of charging current (Icharging_max) is related to the maximum voltage difference, ΔVmax, as follows [32]:…”

“…4(a), depends upon the average power dissipated and absorbed by the capacitors during one complete cycle. It can be calculated as in [28,32]. The typical current and voltage waveforms for these series capacitors are depicted in Fig.…”

“…Since a switch is a combination of Transistor with antiparallel diode, both are considered to calculate losses. Thus, both the losses can be estimated as below [28,32]:…”