Efficiency of body biasing in 90 nm CMOS for low power digital circuits

Arnim, K. von; Borinski, E.; Seegebrecht, P.; Fiedler, H. L.; Brederlow, R.; Thewes, R.; Berthold, J.; Pacha, C.

doi:10.1109/esscir.2004.1356646

Cited by 21 publications

(16 citation statements)

References 3 publications

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“…Hence, onchip real-time monitoring circuit is needed to trace the optimal VBB under the device variation. Some precedent works for monitoring and fixing die-to-die variation by body biasing are reported [3][4][5]. Most of them use drive current monitors, however.…”

Section: Optimal Vbb Scan Under Gidl Effectmentioning

confidence: 98%

On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect

Fujii

Suzuki

Notani

et al. 2008

ESSCIRC 2008 - 34th European Solid-State Circuits Conference

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This paper proposes on-chip leakage monitor circuit to scan optimal reversed body-biasing voltage (VBB) at which leakage current becomes minimal under gate induced drain leakage (GIDL) effect. The proposed circuit determines optimal VBB from the differential measurement of two replica circuit without absolute leakage current measurement. We fabricated this leakage monitor circuit in a 45nm-CMOS process. Measurement results shows 0.1 V resolution of VBB optimization.

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Section: Optimal Vbb Scan Under Gidl Effectmentioning

confidence: 98%

On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect

Fujii

Suzuki

Notani

et al. 2008

ESSCIRC 2008 - 34th European Solid-State Circuits Conference

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“…In fact, early work has showed that buffer delay is minimized when two consecutive sizing factors have a proportion of 3.6 [4], which is also known as the fanout-of-4 rule [16]. Then the actual number of stages associated with this type of buffer can be derived as [16]:…”

Section: Analytical Model For E/d Trade-off Range Explorationmentioning

confidence: 99%

“…However, as technology scales down the margin available for Vt tuning clearly starts decreasing [4][5][6], thus leaving very little margin for delay tuning. For instance, the body effect decreases with every technology generation as a consequence of constant electric field scaling (e.g., thinner oxides, shorter gate lengths and smaller Vth's).…”

Section: Introductionmentioning

confidence: 98%

Synthesis of Runtime Switchable Pareto Buffers Offering Full Range Fine Grained Energy/Delay Trade-Offs

Wang

Catthoor

Miranda

et al. 2007

J Sign Process Syst Sign Image Video Technol

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This paper presents a formalized synthesis methodology for variable tapered buffer chains achieving Pareto optimal Energy-Delay (E/D) trade-offs. Much work has been done for variable tapered buffer chain design explicitly targeting energy (and/or area) minimization for a given timing constraint. In contrast this work presents an automated methodology capable of providing all existing variable tapered buffer configurations achieving Pareto optimal trade-offs in the E/D space for the full feasible range of these two metrics together with a discussion of the practically achievable trade-off range. We also provide a practical case study that illustrates the application of our techniques in load dominated logical blocks such as decoders, drivers in SRAMs and Register Files (RF) as well as interconnect buffers. We have validated our design technique via SPICE simulations based on 65 and 32 nm CMOS technology and applied it for the design and fine tuning of run-time switchable buffers within these blocks, confirming that a very wide range in delay and energy reduction (up to 30%) can be achieved when compared to solely speed optimized buffer design.

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“…For a comparative analysis, it should be noted that the special processes as the FinFET [14], or the floating gate technology [15] as also the bulk-driven technique [7,16], require a very accurate design for a reliable operation [17][18][19][20]. Therefore, some considerations related to standard CMOS design and the clock phases minimization, makes AF-SHA among the most efficient architectures also compared to FOM of the SHA-less analog-to-digital converters (ADCs) [21,22].…”

Section: Introductionmentioning

confidence: 99%

An improved common-mode feedback loop for the differential-difference amplifier

Centurelli

Simonetti

Trifiletti

2012

Analog Integr Circ Sig Process

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Unconditional stability of the high-gain amplifiers is a mandatory requirement for a reliable steady-state condition of time-discrete systems, especially for all blocks designed to sample-and-hold (S/H) circuits. Compared to differential path, the common-mode feedback loop is often affected by poles and zeros shifting that degrades the large signal response of the amplifiers. This drawback is made worse in some well-known topologies as the difference-differential amplifier (DDA) that shows non-constant transconductance and poor linearity. This work proposes a body-driven positive-feedback frequency compensation technique (BD-PFFC) to improve the linearity for precision DDA-based S/H applications. Theoretical calculations and circuit simulations carried out in a 0.13 mu m process are also given to demonstrate its validity

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Efficiency of body biasing in 90 nm CMOS for low power digital circuits

Cited by 21 publications

References 3 publications

On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect

On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect

Synthesis of Runtime Switchable Pareto Buffers Offering Full Range Fine Grained Energy/Delay Trade-Offs

An improved common-mode feedback loop for the differential-difference amplifier

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