Efficient adder circuits based on a conservative reversible logic gate

Bruce, J.W.; Thornton, Mitchell A.; Shivakumaraiah, L.; Kokate, P.S.; Li, Xiaofei

doi:10.1109/isvlsi.2002.1016879

Cited by 123 publications

(117 citation statements)

References 9 publications

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“…It can also be said that the Fredkin gate is zero preserving (once preserving as well) and therefore conservative [15]. Other parity preserving reversible logic gates are 3*3 Feynman Double gate [7] (shown in Fig.…”

Section: Parity Preserving Reversible Gatesmentioning

confidence: 99%

“…The carry-skip adder is usually comparable in speed to the carry look-ahead technique, but it requires less chip area and consumes less power [15]. The Fig.…”

Section: Parity Preserving Reversible Gatesmentioning

confidence: 99%

“…Varying the size of the carry skip blocks can reduce the total worst case delay, since carries generated or absorbed in the adder center have shorter data paths [15]. Without loss of generality, the first and last carry skip blocks are b bits wide, and the carry skip adder is divided into t blocks, where t is even.…”

Section: Variable Block Carry Skip Addermentioning

confidence: 99%

“…Let α = A two input EXOR gate calculation β = A two input AND gate calculation δ= A NOT gate calculation T = Total logical calculation The total logical calculation of the CSA presented in [15] and [17] are T= 48α+96β+24δ and T=40α+28β+12δ respectively. On the contrary, the total logical calculation of the presented CSAs in this study are T=37α+29β+12δ (Fig.…”

Section: Variable Block Carry Skip Addermentioning

confidence: 99%

“…14) and T=34 α+32β+5δ (Fig 15). The presented CSAs require only 13 reversible gates whereas the CSA designs in [15] and [17] require 14 and 24 reversible gates respectively. The presented designs also significantly reduce the required number of constant inputs and garbage outputs.…”

Section: Variable Block Carry Skip Addermentioning

confidence: 99%

See 4 more Smart Citations

Fault Tolerant Variable Block Carry Skip Logic(VBCSL) Using Parity Preserving ReversibleGates

Islam¹,

Rahman²,

Begum³

et al. 2011

IJCEE

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Abstract-Reversible logic design has become one of the promising research directions in low power dissipating circuit design in the past few years and has found its application in low power CMOS design, digital signal processing and nanotechnology. This paper presents the efficient design approaches of fault tolerant carry skip adders (FTCSAs) and compares those designs with the existing ones. Variable block carry skip logic (VBCSL) using the fault tolerant full adders (FTFAs) has also been developed. The designs are minimized in terms of hardware complexity, gate count, constant inputs and garbage outputs. Besides of it, technology independent evaluation of the proposed designs clearly demonstrates its superiority with the existing counterparts.

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Section: Parity Preserving Reversible Gatesmentioning

confidence: 99%

“…The carry-skip adder is usually comparable in speed to the carry look-ahead technique, but it requires less chip area and consumes less power [15]. The Fig.…”

Section: Parity Preserving Reversible Gatesmentioning

confidence: 99%

Section: Variable Block Carry Skip Addermentioning

confidence: 99%

Section: Variable Block Carry Skip Addermentioning

confidence: 99%

Section: Variable Block Carry Skip Addermentioning

confidence: 99%

See 3 more Smart Citations

Fault Tolerant Variable Block Carry Skip Logic(VBCSL) Using Parity Preserving ReversibleGates

Islam¹,

Rahman²,

Begum³

et al. 2011

IJCEE

View full text Add to dashboard Cite

show abstract

Reversible Logic Synthesis

Dueck

Maslov

2020

Reversible and DNA Computing

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A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures

Thapliyal

Srinivas

2005

Advances in Computer Systems Architecture

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In the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. The classical set of gates such as AND, OR, and EXOR are not reversible. This paper proposes a new 4 * 4 reversible gate called "TSG" gate. The proposed gate is used to design efficient adder units. The most significant aspect of the proposed gate is that it can work singly as a reversible full adder i.e reversible full adder can now be implemented with a single gate only. The proposed gate is then used to design reversible ripple carry and carry skip adders. It is demonstrated that the adder architectures designed using the proposed gate are much better and optimized, compared to their existing counterparts in literature; in terms of number of reversible gates and garbage outputs. Thus, this paper provides the initial threshold to building of more complex system which can execute more complicated operations using reversible logic.I.

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Efficient adder circuits based on a conservative reversible logic gate

Abstract: Abstract

Cited by 123 publications

References 9 publications

Fault Tolerant Variable Block Carry Skip Logic(VBCSL) Using Parity Preserving ReversibleGates

Fault Tolerant Variable Block Carry Skip Logic(VBCSL) Using Parity Preserving ReversibleGates

Reversible Logic Synthesis

A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures

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