Efficient encoding of quasi-cyclic low-density parity-check codes

FPGA implementation of highly secure, hardware‐efficient QC‐LDPC code–based nonlinear cryptosystem for wireless sensor networks

“…The QC-LDPC codes are an important class of structured LDPC codes that facilitates low complexity encoding using shift registers and provides good error correction performance. [7][8][9] They can exploit randomness in their design without increase in structural complexity even if the key is changed. In the present work, key-based QC-LDPC code is designed on the basis of extended difference family (EDF) 8 to offer a large key space even for small dimension.…”

“…The major units are (1) nonlinear mapping, (2) encoding unit, (3) key stream generator, (4) permutation unit, (5) controller, (6) select logic, (7) control logic, and (8) memory. In the proposed architecture, parity generation is realized through shift register adder accumulator–based parallel encoding technique . The advantage of using this architecture is that it is suitable for any code rates and can be implemented with reduced number of storage elements when compared to shift register adder accumulator–based serial encoding technique .…”

“…In the proposed work, the generator matrix of key‐based EDF‐QC‐LDPC code in systematic form allows easy encoder implementation using shift registers, so that encoding complexity depends linearly on number of parity bits. For half rate code, to generate ( n ‐ k ) bits of parity, k number of flip flops, k number of 2 input AND gates, and a single k input XOR gate are required.…”

“…9 The advantage of using this architecture is that it is suitable for any code rates and can be implemented with reduced number of storage elements when compared to shift register adder accumulatorbased serial encoding technique. 9 For proper controlling of the sequence of operations, different enable signals EN1, EN2, and EN3 together indicated as EN are generated from the controller. Because the message and key stream are available at different rates, the last n/2 bits of the vector w stored in a buffer as stream z is xor-ed with the k-bit message, once in every n clock cycles according to the enable signal EN1.…”

“…Although random LDPC codes give good degrees of freedom for embedding security, the structural complexity in encoding is high. The QC‐LDPC codes are an important class of structured LDPC codes that facilitates low complexity encoding using shift registers and provides good error correction performance . They can exploit randomness in their design without increase in structural complexity even if the key is changed.…”