Efficient generation of monitor circuits for GSTE assertion graphs

Hu, Alan J.; Cases, J.; Yang, Jin

doi:10.1109/iccad.2003.159685

Cited by 17 publications

(12 citation statements)

References 25 publications

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“…Several approaches [4], [5], [6] integrate assertions into postsilicon checking of hardware by observing its execution trace. In [7], [8], hardware monitors are introduced to ameliorate observability requirements on silicon.…”

Section: ) Memory Usagesmentioning

confidence: 99%

Optimizing post-silicon conformance checking

Cong

Xie

2013

2013 IEEE 31st International Conference on Computer Design (ICCD)

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Abstract-Virtual prototypes of hardware devices, a.k.a, virtual devices, are increasingly used to enable early software development before silicon prototypes/devices are available. In previous work, we presented a post-silicon conformance checking approach to detecting interface state inconsistencies between a silicon device and its virtual device. In this paper, we present an optimization, adaptive concretization, to reduce the overhead incurred by symbolic execution, a key technique used in our conformance checking approach. We have evaluated our optimized approach on three Ethernet adapters and their virtual devices. The results demonstrate that it is effective and efficient: 21 inconsistencies are discovered and time usages are reduced by an order of magnitude, comparing to the previous approach.

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Section: ) Memory Usagesmentioning

confidence: 99%

Optimizing post-silicon conformance checking

Cong

Xie

2013

2013 IEEE 31st International Conference on Computer Design (ICCD)

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“…The construction is rather intricate and is described elsewhere [7]. Here, we give a brief overview.…”

Section: Monitor Circuits From Assertion Graphsmentioning

confidence: 99%

Reasoning about GSTE Assertion Graphs

Casas²,

Yang³

2003

Lecture Notes in Computer Science

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Abstract. Generalized symbolic trajectory evaluation (GSTE) is a new modelchecking approach that combines the industrially-proven scalability and capacity of classical symbolic trajectory evaluation with the expressive power of temporallogic model checking. GSTE was originally developed at Intel and has been used successfully on Intel's next-generation microprocessors. However, the supporting theory and algorithms for GSTE are still immature. In particular, GSTE specifications are given as assertion graphs, a variety of ∀-automata, and although an efficient model-checking algorithm exists to verify whether a circuit model obeys a specification assertion graph, there is no work on reasoning about assertion graphs themselves. This paper presents new algorithms to leverage GSTE model checking to efficiently decide whether one assertion graph implies another, and to model check one assertion graph under the assumption that another is true (under regular GSTE acceptance conditions). These two operations -deciding whether one specification implies another and verifying under an assumption -are the fundamental building blocks of compositional verification and any higher-level reasoning about model-checking results, so the algorithms presented here are key steps to using GSTE in a broader verification framework. Preliminary experimental results applying our algorithms to real, industrial circuits and specifications show that our algorithms are useful in practice.

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“…A notable work is "backspace" [6], it uses SAT-solving techniques to provide an execution trace to a crashed post-silicon state, thus facilitating off-line debugging. Several approaches [3,8,12] integrate formal specifications into post-silicon checking of hardware by observing its execution trace. In [14], hardware monitors are introduced to ameliorate observability requirements on silicon.…”

Section: Related Workmentioning

confidence: 99%

Post-silicon conformance checking with virtual prototypes

Xie

Cong

2013

Proceedings of the 50th Annual Design Automation Conference

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Virtual prototypes are increasingly used in device/driver co-development and co-validation to enable early driver development and reduce product time-to-market. However, drivers developed over virtual prototypes often do not work readily on silicon devices, since silicon devices often do not conform to virtual prototypes. Therefore, it is important to detect the inconsistences between silicon devices and virtual prototypes.We present an approach to post-silicon conformance checking of a hardware device with its virtual prototype, i.e., a virtual device. The conformance between the silicon and virtual devices is defined over their interface states. This approach symbolically executes the virtual device with the same driver request sequence to the silicon device, and checks if the interface states of the silicon and virtual devices are consistent. Inconsistencies detected indicate potential errors in either the silicon device or the virtual device. We have evaluated our approach on three network adapters and their virtual devices, and found 15 inconsistencies exposing 15 real bugs in total from the silicon and virtual devices. The results demonstrate that our approach is useful and efficient in facilitating device/driver covalidation at the post-silicon stage.

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Efficient generation of monitor circuits for GSTE assertion graphs

Cited by 17 publications

References 25 publications

Optimizing post-silicon conformance checking

Optimizing post-silicon conformance checking

Reasoning about GSTE Assertion Graphs

Post-silicon conformance checking with virtual prototypes

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