Efficient lock-free durable sets

Zuriel, Yoav; Friedman, Michal; Sheffi, Gali; Cohen, Nachshon; Petrank, Erez

doi:10.1145/3360554

Cited by 47 publications

(34 citation statements)

References 44 publications

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“…We observe that Px86's asynchronous explicit persist instructions lie in sharp contrast with a variety of previous work and developers' guides, ranging from theory to practice, that assumed, sometimes implicitly, łsynchronousž explicit persist instructions that allow the programmer to assert that certain write must have persisted at certain program points (e.g., [Arulraj et al 2018;Chen and Jin 2015;David et al 2018;Friedman et al 2020Friedman et al , 2018Gogte et al 2018;Izraelevitz et al 2016b;Kolli et al 2017Kolli et al , 2016Lersch et al 2019;Liu et al 2020;Oukid et al 2016;Scargall 2020;Venkataraman et al 2011;Yang et al 2015;Zuriel et al 2019]). For example, Izraelevitz et al [2016b]'s psync instruction blocks until all previous explicit persist institutions łhave actually reached persistent memoryž, but such instruction cannot be implemented in Px86.…”

Section: Introductioncontrasting

confidence: 70%

Taming x86-TSO persistency

Khyzha

Lahav

2021

Proc. ACM Program. Lang.

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We study the formal semantics of non-volatile memory in the x86-TSO architecture. We show that while the explicit persist operations in the recent model of Raad et al. from POPL'20 only enforce order between writes to the non-volatile memory, it is equivalent, in terms of reachable states, to a model whose explicit persist operations mandate that prior writes are actually written to the non-volatile memory. The latter provides a novel model that is much closer to common developers' understanding of persistency semantics. We further introduce a simpler and stronger sequentially consistent persistency model, develop a sound mapping from this model to x86, and establish a data-race-freedom guarantee providing programmers with a safe programming discipline. Our operational models are accompanied with equivalent declarative formulations, which facilitate our formal arguments, and may prove useful for program verification under x86 persistency.

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Section: Introductioncontrasting

confidence: 70%

Taming x86-TSO persistency

Khyzha

Lahav

2021

Proc. ACM Program. Lang.

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“…PMDK transactions of Intel [2015]), as well as other persistent data structures (e.g. sets in [Cooper 2008;PCJ 2016;Zuriel et al 2019]). Recall from ğ7 that a key challenge of testing persistency is that nvo (the persist order) is not directly observable.…”

Section: Related and Future Workmentioning

confidence: 99%

“…persistent memory) will eventually supplant volatile memory, allowing efficient access to persistent data [Intel 2014;ITRS 2011;Pelley et al 2014]. This has led to a surge in NVM research in recent years [Boehm and Chakrabarti 2016;Chakrabarti et al 2014;Chatzistergiou et al 2015;Coburn et al 2011;Gogte et al 2018;Izraelevitz et al 2016a;Kolli et al 2017Nawab et al 2017;Volos et al 2011;Wu and Reddy 2011;Zhao et al 2013;Zuriel et al 2019].…”

Section: Introductionmentioning

confidence: 99%

Persistency semantics of the Intel-x86 architecture

Raad

Wickerson

Neiger

et al. 2019

Proc. ACM Program. Lang.

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Emerging non-volatile memory (NVM) technologies promise the durability of disks with the performance of RAM. To describe the persistency guarantees of NVM, several memory persistency models have been proposed in the literature. However, the persistency semantics of the ubiquitous x86 architecture remains unexplored to date. To close this gap, we develop the Px86 ('persistent x86') model, formalising the persistency semantics of Intel-x86 for the first time. We formulate Px86 both operationally and declaratively, and prove that the two characterisations are equivalent. To demonstrate the application of Px86, we develop two persistent libraries over Px86: a persistent transactional library, and a persistent variant of the MichaelśScott queue. Finally, we encode our declarative Px86 model in Alloy and use it to generate persistency litmus tests automatically.

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“…They place undo log and its logged data structure in the same cache line to reduce CLF. Link-free and soft algorithms [64] implement a durable concurrent set that only persists set members but avoids persisting pointers to eliminate unnecessary CLF. Software Cache [36] implements a resizable cache to combine writebacks and reduce CLF.…”

Section: Related Workmentioning

confidence: 99%

Ribbon

Ren

Liu

2020

Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques

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Cache line flushing (CLF) is a fundamental building block for programming persistent memory (PM). CLF is prevalent in PM-aware workloads to ensure crash consistency. It also imposes high overhead. Extensive works have explored persistency semantics and CLF policies, but few have looked into the CLF mechanism. This work aims to improve the performance of CLF mechanism based on the performance characterization of well-established workloads on real PM hardware. We reveal that the performance of CLF is highly sensitive to the concurrency of CLF and cache line status. We introduce Ribbon, a runtime system that improves the performance of CLF mechanism through concurrency control and proactive CLF. Ribbon detects CLF bottleneck in oversupplied and insufficient concurrency, and adapts accordingly. Ribbon also proactively transforms dirty or non-resident cache lines into clean resident status to reduce the latency of CLF. Furthermore, we investigate the cause for low dirtiness in flushed cache lines in in-memory database workloads. We provide cache line coalescing as an applicationspecific solution that achieves up to 33.3% (13.8% on average) improvement. Our evaluation of a variety of workloads in four configurations on PM shows that Ribbon achieves up to 49.8% improvement (14.8% on average) of the overall application performance. CCS CONCEPTS • Hardware → Emerging technologies; • Computer systems organization → Multicore architectures; • Software and its engineering → Concurrency control.

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Efficient lock-free durable sets

Cited by 47 publications

References 44 publications

Taming x86-TSO persistency

Taming x86-TSO persistency

Persistency semantics of the Intel-x86 architecture

Ribbon

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