Efficient Realization of Parity Prediction Functions in FPGAs

Ko, Seok‐Bum; Lo, Jien-Chung

doi:10.1023/b:jett.0000042513.15382.e7

Cited by 11 publications

(14 citation statements)

References 14 publications

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“…In contrast to [16], positive Davio and negative Davio decomposition are additionally utilized. It has been shown that the usage of positive Davio and negative Davio leads to optimization in classical circuit synthesis [18], [19], [20]. We show why the usage of these decomposition types offers several advantages during synthesis especially when working with reversible gates.…”

Section: Introductionmentioning

confidence: 83%

Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition

Soeken

Wille

Drechsler

2010

2010 5th International Design and Test Workshop

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Abstract-Synthesis of reversible circuits is an important research area providing the basis for a design flow of this emerging technology. Recently, in the development of scalable synthesis approaches a significant step forward has been made by a hierarchical method in combination with Shannon decomposition. However, this approach leads to circuits with high costs. In this paper, we propose an alternative that additionally makes use of positive Davio and negative Davio decomposition. We show that the usage of these decomposition types offers several advantages for the synthesis of reversible circuits. Using the proposed approach, on average the number of lines can be reduced by 22%, the number of gates by 22%, and the quantum cost by 32%. In the best case, even reductions of more than 60% are possible.

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Section: Introductionmentioning

confidence: 83%

Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition

Soeken

Wille

Drechsler

2010

2010 5th International Design and Test Workshop

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“…Systematic codes, like Berger codes and parity groups, are very interesting as the original bits are not altered, which alleviates the decoding of outputs in the original datapath. Equally important, conditions for fault security in parity predictors (outputs are either correct or form an invalid code word) were derived in [14], and a generic optimisation technique for parity prediction functions to achieve fast and small circuits was presented in [15]. Accordingly, a detailed low level view of the proposed architecture is depicted in Figure 2.…”

Section: Fugacious Fault Modelsmentioning

confidence: 99%

Increasing the Dependability of VLSI Systems through Early Detection of Fugacious Faults

Espinosa

Andrés

Gil

2015

2015 11th European Dependable Computing Conference (EDCC)

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Abstract-Technology advances provide a myriad of advantages for VLSI systems, but also increase the sensitivity of the combinational logic to different fault profiles. Shorter and shorter faults which up to date had been filtered, named as fugacious faults, require new attention as they are considered a feasible sign of warning prior to potential failures. Despite their increasing impact on modern VLSI systems, such faults are not largely considered today by the safety industry. Their early detection is however critical to enable an early evaluation of potential risks for the system and the subsequent deployment of suitable failure avoidance mechanisms. For instance, the early detection of fugacious faults will provide the necessary means to extend the mission time of a system thanks to the temporal avoidance of aging effects. Because classical detection mechanisms are not suited to cope with such fugacious faults, this paper proposes a method specifically designed to detect and diagnose them. Reported experiments will show the feasibility and interest of the proposal.

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“…In [22] conditions for fault secureness in parity predictors are derived. Furthermore [23] presents a generic optimisation technique for parity prediction functions, to achieve quick and small circuits.…”

Section: Architecture Of a Faults Detection And Discrimination Systemmentioning

confidence: 99%

The Challenge of Detection and Diagnosis of Fugacious Hardware Faults in VLSI Designs

Espinosa

Andrés

Ruíz

et al. 2013

Lecture Notes in Computer Science

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Abstract. Current integration scales are increasing the number and types of faults that embedded systems must face. Traditional approaches focus on dealing with those transient and permanent faults that impact the state or output of systems, whereas little research has targeted those faults being logically, electrically or temporally masked -which we have named fugacious. A fast detection and precise diagnosis of faults occurrence, even if the provided service is unaffected, could be of invaluable help to determine, for instance, that systems are currently under the influence of environmental disturbances like radiation, suffering from wearout, or being affected by an intermittent fault. Upon detection, systems may react to adapt the deployed fault tolerance mechanisms to the diagnosed problem. This paper explores these ideas evaluating challenges and requirements involved, and provides an outline of potential techniques to be applied.

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Efficient Realization of Parity Prediction Functions in FPGAs

Cited by 11 publications

References 14 publications

Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition

Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition

Increasing the Dependability of VLSI Systems through Early Detection of Fugacious Faults

The Challenge of Detection and Diagnosis of Fugacious Hardware Faults in VLSI Designs

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