Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction

Gulati, Kanupriya; Waghmode, Mandar; Khatri, Sunil P.; Shi, Weiping

doi:10.1049/iet-cdt:20060221

Cited by 13 publications

(8 citation statements)

References 10 publications

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“…A radical approach is taken in [14], which developed a custom integrated-circuit cell just for BCP. As if SRAM is too slow, they store the SAT problem in registers.…”

Section: B Modern Hardware Sat Acceleratorsmentioning

confidence: 99%

FPGA acceleration of enhanced boolean constraint propagation for SAT solvers

Thong¹,

Nicolici²

2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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We propose a hardware architecture to accelerate boolean constraint propagation (BCP). Although satisfiability (SAT) solvers in software use varying search and learning strategies, BCP is a fundamental component and by far consumes the most CPU time. Our field-programmable gate array (FPGA) design uses on-chip SRAM to facilitate the acceleration of BCP. We discuss many insights to our innovative hardware memory layout, which is very compact and enables extremely fast BCP. It also supports multithreading to minimize the idle time in hardware and to fully utilize the multicore processor host. Additionally, many industrial SAT instances encode logic gates as constraints. We compact these to simultaneously reduce the hardware memory usage as well as speed up the computation (enhanced BCP). We implemented our enhanced BCP core and integrated it with a simple software SAT solver which communicates over PCI Express. Hardware performance counters show that a single processing engine is up to 4x faster than a state-of-the-art software SAT solver.

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“…A radical approach is taken in [14], which developed a custom integrated-circuit cell just for BCP. As if SRAM is too slow, they store the SAT problem in registers.…”

Section: B Modern Hardware Sat Acceleratorsmentioning

confidence: 99%

FPGA acceleration of enhanced boolean constraint propagation for SAT solvers

Thong¹,

Nicolici²

2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…A custom ASIC implementation of a Boolean satisfiability solver was presented in Gulati et al [2008]. Our current approach is an FPGA version of Gulati et al [2008].…”

Section: Previous Workmentioning

confidence: 99%

“…Our current approach is an FPGA version of Gulati et al [2008]. However, the custom ASIC approach solves the entire instance in a monolithic fashion.…”

Section: Previous Workmentioning

confidence: 99%

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FPGA-based hardware acceleration for Boolean satisfiability

Gulati

Paul

Khatri

et al. 2009

ACM Trans. Des. Autom. Electron. Syst.

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We present an FPGA-based hardware solution to the Boolean satisfiability (SAT) problem, with the main goals of scalability and speedup. In our approach the traversal of the implication graph as well as conflict clause generation are performed in hardware, in parallel. The experimental results and their analysis, along with the performance models are discussed. We show that an order of magnitude improvement in runtime can be obtained over MiniSAT (the best-in-class software based approach) by using a Virtex-4 (XC4VFX140) FPGA device. The resulting system can handle instances with as many as 10K variables and 280K clauses.

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“…Such a SAT-instance represents a Boolean formula (coming from a verification task) and raises the question whether an assignment to all Boolean variables exists such that the overall formula is satisfied (SAT) or remains unsatisfied (UNSAT), respectively. Other existing approaches for SAT-solving either focus on accelerating a SW-based SAT-solver by outsourcing the solving process partially to HW [2,8,13,14] or by introducing even for small SAT-instance sizes a large HW-overhead [9,12]. In contrast to this, the proposed HW SAT-solver is very compact and can be easily integrated as an IP-component into an existing design.…”

Section: Introductionmentioning

confidence: 99%

SAT-Lancer

Ustaoglu

Huhn

Große

et al. 2018

Proceedings of the 2018 Great Lakes Symposium on VLSI

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To close the ever widening verification gap, new powerful solutions are strictly required. One such promising approach aims in continuing verification tasks after production of a chip during its lifetime. This approach is called self-verification. However, for realizing self-verification tasks on-chip, verification packages have to be developed. In this paper, we propose the verification package SATLancer. SAT-Lancer is a compact Boolean Satisfiability (SAT) solver and has been implemented entirely on HW with the capability of solving any arbitrary SAT-instance. At the heart of SAT-Lancer is a scalable memory model, which can be adjusted to given memory constraints and allows to store the SAT-instance most effectively. In comparison to previous HW SAT-solvers, SAT-Lancer utilizes significant less area and can handle order of magnitude larger SATinstances.

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Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction

Cited by 13 publications

References 10 publications

FPGA acceleration of enhanced boolean constraint propagation for SAT solvers

FPGA acceleration of enhanced boolean constraint propagation for SAT solvers

FPGA-based hardware acceleration for Boolean satisfiability

SAT-Lancer

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