Efficient scheduling scheme for eight-parallel MDC FFT processor

Jang, Jeong Keun; Kim, Moon Gi; Sunwoo, Myung Hoon

doi:10.1109/isocc.2015.7401755

Cited by 8 publications

(3 citation statements)

References 5 publications

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Order By: Relevance

“…As an example, let us consider the order 0123|45 at stage 1 and the sequence of orders [45,34,43,12,21,10] for the parallel dimensions. Then, the orders of the FFT are according to Table V.…”

Section: Feasible Orders In Optimum MDC Fftsmentioning

confidence: 99%

Optimum MDC FFT Hardware Architectures in Terms of Delays and Multiplexers

Garrido

Paz

2021

IEEE Trans. Circuits Syst. II

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In this paper, we show how to derive all the optimum multi-path delay commutator (MDC) fast Fourier transform (FFT) hardware architectures in terms of delays and multiplexers and calculate the number of such architectures. The proposed approach is based on analyzing the orders at the FFT stages that lead to optimum number of delays and multiplexers. The results show that there exist a large number of optimum MDC FFTs. This large design space can be explored in the future in order to design efficient MDC architectures that not only optimize the number of delays and multiplexers, but also other figures of merit such as the number of rotators or the input/output data order.

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Section: Feasible Orders In Optimum MDC Fftsmentioning

confidence: 99%

Optimum MDC FFT Hardware Architectures in Terms of Delays and Multiplexers

Garrido

Paz

2021

IEEE Trans. Circuits Syst. II

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“…This corresponds to a circle of radius 2 q ε around P OP T (α). Note that the maximum error ε that defines the circle is calculated from W L E according to (6). Additionally, we include the condition that the the magnitude of the coefficients must be smaller than or equal to 2 q .…”

Section: A Design Of the Rotatorsmentioning

confidence: 99%

World’s Fastest FFT Architectures: Breaking the Barrier of 100 GS/s

Garrido

Möller

Kumm

2019

IEEE Trans. Circuits Syst. I

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“…In a real-time SAR system, an FFT processor should provide high throughput rates. Therefore, the MDC architecture is more appropriate than the SDF architecture in such systems [41,42].…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of the Range-Doppler Algorithm for Real-Time Synthetic Aperture Radar Imaging

et al. 2021

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In this paper, we propose a range-Doppler algorithm (RDA)-based synthetic aperture radar (SAR) processor for real-time SAR imaging and present FPGA-based implementation results. The processing steps for the RDA include range compression, range cell migration correction (RCMC), and azimuth compression. A matched filtering unit (MFU) and an RCMC processing unit (RPU) are required for real-time processing. Therefore, the proposed RDA-based SAR processor contains an MFU that uses the mixed-radix multi-path delay commutator (MRMDC) FFT and an RPU. The MFU reduces the memory requirements by applying a decimation-in-frequency (DIF) FFT and decimation-in-time (DIT) IFFT. The RPU provides a variable tap size and variable interpolation kernel. In addition, the MFU and RPU are designed to enable parallel processing of four 32-bit which are transferred via a 128-bit AXI bus. The proposed RDA-based SAR processor was designed using Verilog-HDL and implemented in a Xilinx UltraScale+ MPSoC FPGA device. After comparing the execution time taken by the proposed SAR processor with that taken by an ARM cortex-A53 microprocessor, we observed a 85-fold speedup for a 2048 × 2048 pixel image. A performance evaluation based on related studies indicated that the proposed processor achieved an execution time that was approximately 6.5 times less than those of previous FPGA implementations of RDA processors.

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Efficient scheduling scheme for eight-parallel MDC FFT processor

Cited by 8 publications

References 5 publications

Optimum MDC FFT Hardware Architectures in Terms of Delays and Multiplexers

Optimum MDC FFT Hardware Architectures in Terms of Delays and Multiplexers

World’s Fastest FFT Architectures: Breaking the Barrier of 100 GS/s

FPGA Implementation of the Range-Doppler Algorithm for Real-Time Synthetic Aperture Radar Imaging

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