Efficient VLSI Architecture for Fuzzy C-Means Clustering in Reconfigurable Hardware

Abstract

A cost-effective parallel VLSI architecture for fuzzy c-means clustering is presented. The architecture reduces the area cost and computational complexity for membership coefficients and centroid computation by employing lookup table based dividers. The usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. Experimental results show that the proposed solution is an effective alternative for cluster analysis with low computational cost and high performance.

Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning

“…In addition, they are implemented on different FPGA devices. However, it can still be observed from the table that the proposed architecture has lower area costs as compared with the architectures in [34,35]. In addition, with larger training set and number of clusters, the architecture is able to perform the clustering with less computational time as compared with the architecture in [35].…”

“…The architectures in [34,35] are pipelined circuits for c -means and fuzzy c means algorithms, respectively. All the architectures have the same dimension w = 2 × 2.…”

Efficient Fuzzy C-Means Architecture for Image Segmentation

“…However, most of these algorithms are implemented by software, and only moderate acceleration can be achieved. In [ 9 – 11 ], hardware implementations of FCM are proposed. Nevertheless, the design in [ 9 ] is based on analog circuits.…”

“…In addition, it may be difficult to extend the architecture for the hardware implementation of FCM-S. The architecture presented in [ 11 ] operates with only a fixed degree of fuzziness m = 2 for the original FCM. The flexibility for selecting other degrees of fuzziness may be desired to further improve the FCM performance.…”

“…The flexibility for selecting other degrees of fuzziness may be desired to further improve the FCM performance. In addition, similar to [ 10 ], the architecture presented in [ 11 ] cannot be directly used for the hardware implementation of FCM-S.…”