Elastic Flow in an Application Specific Network-on-Chip

Gebhardt, Daniel; Stevens, Kenneth S.

doi:10.1016/j.entcs.2008.02.003

Cited by 10 publications

(6 citation statements)

References 16 publications

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“…We used a method extended from [33] that uses force-directed movement to provide router locations and link lengths to the SA process. Force vectors are applied to routers that are proportional to: (a) bandwidth requirements and (b) physical distances between the router and its attached core or router.…”

Section: A Topology and Placementmentioning

confidence: 99%

Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs

Gebhardt

You

Stevens

2010

2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip

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Abstract-Power consumption of on-chip interconnects is a primary concern for many embedded system-on-chip (SoC) applications. In this paper, we compare energy and performance characteristics of asynchronous (clockless) and synchronous networkon-chip implementations, optimized for a number of SoC designs. We adapted the COSI-2.0 framework with ORION 2.0 router and wire models for synchronous network generation. Our own tool, ANetGen, specifies the asynchronous network by determining the topology with simulated-annealing and router locations with force-directed placement. It uses energy and delay models from our 65 nm bundled-data router design. SystemC simulations varied traffic burstiness using the self-similar b-model. Results show that the asynchronous network provided lower median and maximum message latency, especially under bursty traffic, and used far less router energy with a slight overhead for the interrouter wires.

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Section: A Topology and Placementmentioning

confidence: 99%

Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs

Gebhardt

You

Stevens

2010

2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip

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“…I-E performed better for some applications while I/E generated better results for other. Moreover, the custom topologies generated from algorithms 1-4 performed better over the energy efficient mapping of cores onto standard structures like mesh and binary tree presented in [5], [7]. Similar procedure could be followed for a latency and bandwidth constrained graph with effective weights calculated using heuristic presented in section 3.E.…”

Section: Resultsmentioning

confidence: 94%

“…We calculated the power consumption for VOPD, H.264 Decoder, MPEG4 Decoder, MWD, H.263 enc MP3 enc and H.263 dec MP3 dec, which are commonly used benchmarks, onto the following topologies: 1)Modified Greedy Binary Tree 2)EquiMinCut-MappingTree 3)I-E Heuristic Tree 4)I/E Heuristic Tree obtained from the aforementioned algorithms and compared with Modified Complete Binary Tree [7], Star and MOCA optimal Mesh [5].…”

Section: Power Analysismentioning

confidence: 99%

Low Energy Tree Based Network on Chip Architectures Using Homogeneous Routers for Bandwidth and Latency Constrained Multimedia Applications

Majeti

Pasalapudi²,

Yalamanchili

2009

2009 Second International Conference on Emerging Trends in Engineering &Amp; Technology

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Design of Network on chip architectures for multimedia applications is being widely studied. This involves design decisions at various levels of hierarchy. Topology design is one of the significant factors that affect the net delay and the energy consumption of the system. Most of the applications are characterized by bandwidth requirements and latency constraints. The topology must be built satisfying these constraints. The paper aims in generating low energy tree based topologies using homogeneous routers for bandwidth and latency constrained applications.

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“…The initial topology is a balanced tree, where a heuristic maps cores to leaves [1]. Force-directed placement is done to complete the initial solution.…”

Section: Evaluation and Resultsmentioning

confidence: 99%