Electrical Comparison of ${\rm HfO}_{2}$ and ${\rm ZrO}_{2}$ Gate Dielectrics on GaN

Effects of Post-Deposition Annealing on ZrO2/n-GaN MOS Capacitors with H2O and O3 as the Oxidizers

“…Many high- k materials such as Al 2 O 3 [10], ZrO 2 [11], MgO [12], and TiO 2 [13] have been investigated for GaN-based MOS capacitors. Among them, ZrO 2 is attractive because it has a high permittivity (~24), large bandgap (5.8 eV), and more importantly, an appropriate value of band offset with GaN (valance band offset ~1.6 eV, conduction band offset ~1.1 eV) [14].…”

“…In terms of dielectric films, high- k oxides are always among the candidates, because the high dielectric constant means much smaller featured size and lower power consumption [ 8 , 9 ]. Many high- k materials such as Al 2 O 3 [ 10 ], ZrO 2 [ 11 ], MgO [ 12 ], and TiO 2 [ 13 ] have been investigated for GaN-based MOS capacitors. Among them, ZrO 2 is attractive because it has a high permittivity (~24), large bandgap (5.8 eV), and more importantly, an appropriate value of band offset with GaN (valance band offset ~1.6 eV, conduction band offset ~1.1 eV) [ 14 ].…”

Ultra low density of interfacial traps with mixed thermal and plasma enhanced ALD of high-κ gate dielectrics

“…The detailed description of the deposition procedure can be found in previous publications. 8,9,32 Substrate temperature was maintained at 100 C and chamber pressure was kept at 1.07 Torr during thin lm growth. Tetrakis(dimethylamido)-zirconium (Sigma-Aldrich >99.99%) and tetrakis(dimethylamido)hafnium (Sigma-Aldrich >99.99%) were utilized as precursor for zirconium and hafnium, respectively.…”

“…6,7 However, the ultra-low density of interfacial traps (D it $ 10 10 cm À2 eV À1 ) found at the Si/SiO 2 interface is difficult to achieve at the deposited high-k dielectric/ Si interface mainly due to large differences in the atomic crystal coordinates of silicon and high-k oxides. 8,9 The semiconductorgate dielectric interface is one of the most crucial regions of a MOS device. 8,10 Deposited high-k oxide thin lms replaced thermally grown SiO 2 in silicon MOS devices due to scaling issues with SiO 2 as a gate dielectric.…”

“…8,9 The semiconductorgate dielectric interface is one of the most crucial regions of a MOS device. 8,10 Deposited high-k oxide thin lms replaced thermally grown SiO 2 in silicon MOS devices due to scaling issues with SiO 2 as a gate dielectric. 7,11 For III-V compound devices, where there are no good quality semiconductor native oxides, a deposited gate oxide is the only option.…”