Electro-Thermomigration in NMOS LSI Devices

DeChiaro, L.F.

doi:10.1109/irps.1981.363001

Cited by 11 publications

(2 citation statements)

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“…For example, Figure 2 shows the fused polysilicon resistor of the input protection circuit of a ( ' M ( 1 S in i c r o p rocc s so r ; more d e t a i 1 e d an a I y s i s , (g) A proposed failure mechanism of ICs clamaged by ESD is electro-thermo-tnigration ( E T M ) of aluminium. 4 We have found that this tvpe of damage can be simulated using a curve tracer. thereby providing an additional method for locating ESD damage sites.…”

Section: A Practical Failure Analysis Methodology For Identifying Esdmentioning

confidence: 94%

A failure analysis methodology for revealing esd damage to integrated circuits

Taylor

Woodhouse

Feasey

1985

Quality & Reliability Eng

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A range of chemical and physical techniques is required in order to identify the failure sites and failure mchanisms of ICs subjected to ESD transients. The damage features of ESD failures from the field are shown to be similar to those produced by simulated human-body-model testing. A curve tracer technique can be used to predict the location of an ESD failure site in the input or output circuit of an IC. Junction shorts induced by ESD transients form as a result of a combination of heating at the site of second breakdown, together with the heat generated by the discharge current in the discharge path. The ESD sensitivity of a given input or output circuit is dependent on the spacing between the input contact window. and the contact window of the nearest diffusion-to-Vss metallization. KEY WORDS Electrostatic damage Integrated circuit failure analysis * Presented at the 6th annual International EOSIESD Symposium, 1984. Reproduced with the permission of the EOS/ESD Association, P 0 Box 298, Westmoreland, NY 13490, U.S.A.

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Section: A Practical Failure Analysis Methodology For Identifying Esdmentioning

confidence: 94%

A failure analysis methodology for revealing esd damage to integrated circuits

Taylor

Woodhouse

Feasey

1985

Quality & Reliability Eng

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“…Failures are accelerated by elevated ambient temperatures in the neighborhood of 400°C. Contact migration is a major cause of failure in (GaAs) devices [DeChairo 1981, Christou 1982, Ballamy 1978, Christou 1980. This failure mechanism may be dominant during VLSI manufacture and packaging when temperatures exceed 400°C.…”

Section: Contact Spikingmentioning

confidence: 99%

The Influence of Temperature on Microelectronic Device Failure Mechanisms. Phase 2

Pecht¹

1993

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Electrostatic discharge: mechanisms, protection techniques and effects on integrated circuit reliability

Avery

1985

Quality & Reliability Eng

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Electrostatic discharge (ESD) was once considered a problem only for unprotected, insulated-gate field-effect transistors, but the ever shrinking geometries of all semiconductor devices have made them vulnerable to this phenomenon. ESD models and on-chip device protection techniques are reviewed, together with current evidence concerning latent defects and their effect on device reliability. A brief discussion on the importance of ESD controls in the assembly environment is also included, with an emphasis on realistic cost-effective measures. Finally, the impact of continued scaling on ESD vulnerability and protection structure limitations, are examined.

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Electro-Thermomigration in NMOS LSI Devices

Cited by 11 publications

References 0 publications

A failure analysis methodology for revealing esd damage to integrated circuits

A failure analysis methodology for revealing esd damage to integrated circuits

The Influence of Temperature on Microelectronic Device Failure Mechanisms. Phase 2

Electrostatic discharge: mechanisms, protection techniques and effects on integrated circuit reliability

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