Electron temperature in electrically isolated Si double quantum dots

We present Silver-epoxy filters combining excellent microwave attenuation with efficient wire thermalization, suitable for low temperature quantum transport experiments. Upon minimizing parasitic capacitances, the attenuation reaches ≥ 100 dB above ≈ 150 MHz and -when capacitors are added -already above ≈ 30 MHz. We measure the device electron temperature with a GaAs quantum dot and demonstrate excellent filter performance. Upon improving the sample holder and adding a second filtering stage, we obtain electron temperatures as low as 7.5 ± 0.2 mK in metallic Coulomb blockade thermometers.

mentioning

confidence: 99%

Silver-epoxy microwave filters and thermalizers for millikelvin experiments

Scheller

Heizmann

Bedner

et al. 2014

“…Remote detection has, therefore, made it unnecessary to have an electrical current flow and has led to the realization of systems in which only one lead or none is used [12,[15][16][17][18][19][20][21]. While the absence of 2DEG reservoirs can be beneficial to both suppress thermal fluctuations induced by electrical noise [22,23] and conveniently scale up these systems, hysteretic behaviour is observed that may complicate the tuning of charge states [24,25]. Such hysteresis can, however, be exploited for the implementation of single-electron memory devices [26,27].…”

mentioning

confidence: 99%

Charge state hysteresis in semiconductor quantum dots

Yang¹,

Rossi²,

Lai³

et al. 2014

Self Cite

Semiconductor quantum dots provide a two-dimensional analogy for real atoms and show promise for the implementation of scalable quantum computers. Here, we investigate the charge configurations in a silicon metal-oxide-semiconductor double quantum dot tunnel coupled to a single reservoir of electrons. By operating the system in the few-electron regime, the stability diagram shows hysteretic tunnelling events that depend on the history of the dots charge occupancy. We present a model which accounts for the observed hysteretic behaviour by extending the established description for transport in double dots coupled to two reservoirs. We demonstrate that this type of device operates like a single-electron memory latch.Keywords: quantum dots, silicon, nanoelectronics, quantum computing.In the last three decades lithographically defined semiconductor quantum dots have been the focus of extensive research efforts [1][2][3], and have attracted large interest for a number of applications, such as solid-state quantum computing [4], quantum dot cellular automata [5][6][7], quantum electrical metrology [8], as well as cryogenic temperature measurement [9] and regulation [10]. The electrical properties of these systems are typically investigated either via electron transport between two-dimensional electron gas (2DEG) reservoirs tunnel coupled to the dots [11] or by detecting charge and spin states with on-chip electrometers [12]. In the context of quantum computing, the use of charge sensing has become the method of choice to perform non-invasive measurements of the coherent quantum bit states that exist in the dots [13,14]. Remote detection has, therefore, made it unnecessary to have an electrical current flow and has led to the realization of systems in which only one lead or none is used [12,[15][16][17][18][19][20][21]. While the absence of 2DEG reservoirs can be beneficial to both suppress thermal fluctuations induced by electrical noise [22,23] and conveniently scale up these systems, hysteretic behaviour is observed that may complicate the tuning of charge states [24,25]. Such hysteresis can, however, be exploited for the implementation of single-electron memory devices [26,27].Here, we investigate a silicon double quantum dot (DQD) that is tunnel-coupled to a single 2DEG reservoir and capacitively coupled to a single-electron transistor (SET) used to detect individual charge transitions in the DQD. When the system is operated in the few-electron regime the stability diagram reveals hysteresis in the DQD occupancy, with the occurrence of charge transitions depending upon the history of the charge states. We present a model that accounts for the characteristic features observed by extending the conventional description of electron transport through double-lead DQDs [2]. We also show that this system functions as a single-electron Set/Reset (S/R) memory latch.Our devices are metal-oxide-semiconductor (MOS) planar structures fabricated on a high-purity, near-intrinsic natural silicon substrate. Three layers of Al/Al y O ...

“…Typically, non-invasive and sensitive charge readout is achieved by means of on-chip electrometers 1,2 . The scope of applicability of these sensing techniques is quite broad, ranging from charge noise characterization [3][4][5] to cryogenic thermometry [6][7][8] , as well as Maxwell's demon implementations 9,10 and quantum metrology [11][12][13] . Arguably, one of the research fields that has more largely benefitted from advancements in charge sensing is solid-state quantum information processing [14][15][16][17][18] .…”

mentioning

confidence: 99%

Dispersive readout of a silicon quantum dot with an accumulation-mode gate sensor

Rossi

Zhao

Dzurak

et al. 2017

Self Cite

Sensitive charge detection has enabled qubit readout in solid-state systems. Recently, an alternative to the well-established charge detection via on-chip electrometers has emerged, based on in situ gate detectors and radio-frequency dispersive readout techniques. This approach promises to facilitate scalability by removing the need for additional device components devoted to sensing. Here, we perform gate-based dispersive readout of an accumulation-mode silicon quantum dot. We observe that the response of an accumulation-mode gate detector is significantly affected by its bias voltage, particularly if this exceeds the threshold for electron accumulation. We discuss and explain these results in light of the competing capacitive contributions to the dispersive response.Reliable measurements of the charge state of nanoscale electronic devices may represent a key ingredient for the realization of future quantum technologies. Typically, non-invasive and sensitive charge readout is achieved by means of on-chip electrometers 1,2 . The scope of applicability of these sensing techniques is quite broad, ranging from charge noise characterization 3-5 to cryogenic thermometry 6-8 , as well as Maxwell's demon implementations 9,10 and quantum metrology 11-13 . Arguably, one of the research fields that has more largely benefitted from advancements in charge sensing is solid-state quantum information processing [14][15][16][17][18] .Recently, an alternative approach to implement charge readout has emerged based on radio-frequency (rf) resonant circuit techniques [19][20][21] . Using in-situ gate electrodes embedded into LC resonators, fast and sensitive charge detection has been attained 22-25 by measuring the dispersive shift of the resonator frequency when electron tunneling occurs. In addition to providing much higher bandwidth than standard electrometry, gate-based reflectometry has an enormous potential for realizing scalable quantum architectures. In fact, a number of proposals has been already put forward to exploit high frequency techniques to different extents [26][27][28][29][30][31] .Lately, spin-based qubits have been realised in planar silicon-based accumulation-mode quantum dots 18,32,33 . Gate-based dispersive readout may be an appealing technique to scale these systems up.In fact, CMOS-compatible architectures have been recently proposed 27,28 which identify routes toward large scalability of silicon-based spin qubit systems. The suggested readout protocol crucially relies on the gate-based dispersive technique discussed here. It has, therefore, become topical to understand its operational boundaries or limitations. In the specific case of accumulation-mode devices, it has been proposed that the same gate(s) used to define the qubit(s) may be used for dispersive readout 26,27 . This would require operating the gate(s) above threshold voltage. However, one has to be aware that the gate capacitance may significantly vary upon bias voltage and, in some circumstances, its contribution may dominate over the tunnelin...