Embedded Wafer Level Ball Grid Array (eWLB)

Brunnbauer, Markus; Meyer, Tyler; Ofner, G.; Mueller, Kurt; Hagen, Ronald

doi:10.1109/eptc.2008.4763559

Cited by 147 publications

(35 citation statements)

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“…The resistance of a hollow round via of depth l and inner and outer diameters d 1 and d 2 , respectively, can be calculated using the known formulas for DC and AC: via for for (1) where σ is the conductivity of the filling metal and δ is the skin depth. The expression for AC assumes that the skin effect is fully developed and the current flows through a thin layer on the outer surface of the metallic cylinder.…”

Section: (B)mentioning

confidence: 99%

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Vertical interconnections using through encapsulant via (TEV) and through silicon via (TSV) for high-frequency system-in-package integration

Wojnowski

Pressel

Beer

et al. 2014

2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)

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In this paper we investigate two vertical interconnect options for high-frequency system-in-package (SiP) integration: through encapsulant via (TEV) applied to the embedded wafer level ball grid array (eWLB) technology and through silicon via (TSV). We compare both solutions in terms of size and electrical performance. We use analytic expressions and electromagnetic simulations for our analysis and present measurement results of selected structures for verification. The results show that the choice of TEV and TSV depends on application and cost window

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Section: (B)mentioning

confidence: 99%

“…Among them are time to market, cost, and performance. During recent years the embedded wafer level ball grid array (eWLB) package has been introduced [1,2]. The eWLB has demonstrated to be an excellent platform for system integration with excellent high-frequency performance.…”

mentioning

confidence: 99%

Vertical interconnections using through encapsulant via (TEV) and through silicon via (TSV) for high-frequency system-in-package integration

Wojnowski

Pressel

Beer

et al. 2014

2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)

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“…Suitable fabrication procedures to receive specimens were demonstrated before [7]. To fabricate our samples we used the wafer level molding equipment from the production of embedded wafer level ball grid arrays (eWLB, [8], [9]). A sandwich structure can be achieved using two mold steps.…”

Section: Sample Fabrication and Experimental Proceduresmentioning

confidence: 99%

Interfacial fracture parameters of silicon-to-molding compound

Schlottig

Maus

Walter

et al. 2010

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)

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The rapid diversification in microelectronics forebodes more complex system integration, be it for denser function integration or a span of dimensions between various technologies. Products may include more features, perform faster and be cheaper. With these trends the amount of material layers is increasing. This challenges development to a faster rating of material pairings. Delamination is a major issue among the related reliability aspects. When the design or testing steps are accompanied by simulation, fracture mechanical descriptions are increasingly proving helpful. The parameters needed for simulation have to be measured and should be available for different fracture mode mix angles. We investigated the interfacial fracture toughness of the Epoxy Molding Compound (EMC) to Silicon interface. Although difficult to delaminate we could carry out measurements using the Mixed Mode Chisel setup (MMC) that allowed us to induce different stress states at the crack tip at various external load angles. The samples we derived from the molding process of embedded wafer level ball grid arrays. Therefore we were able to use samples made with the same process as in real packaging. The crack tip position was determined by analysis of displacement results by digital image correlation. In order to interpret the sample reaction for extracting fracture mechanical parameters, adequate numerical modeling and simulation was required. The experiments provided the parameters for the models. Establishing the residual stress state in the materials preceded the interface delamination simulation: a two step interpretation. Residual stresses cannot be neglected; indeed they are part of the challenges to delaminate this interface at all. We found energy release rates increasing with fracture mode mix, and such values close to pure tensile opening at the crack tip. We recommend to exclude data from short crack lengths and to carefully expose the sample flanks. The results promise to extend - - the available interfacial fracture data soon

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“…A very promising technology derived from ball less MAP-type molding is the embedded Wafer Level BGA (eWLB) approach [4,5]. Both encapsulation technologies, MAP-type molding as well as eWLB, combine the overmolding of large areas (£ = 25-100 mm) with a relatively thin mold cover (height < 1 mm).…”

Section: Introduction: Map-type Overmoldingmentioning

confidence: 99%