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This paper presents stress measurements in leadframe based QFN components due to fabrication and assembly processes, characterized by substitution with stress measurement chips. The results are based on a method to determine stresses within electronic components by use of on-chip CMOS stress measurement technology, realized during the BMBF funded project iForceSens. All relevant production steps have been investigated. Four different chip and package sizes have been studied. Typical stress states will be compared with warpage and delamination analysis. The stress sensor is based on a CMOS chip. Although it is subdivided into 60 measurement cells (300 m grid) the sensor needs only four electrical connections. This alignment allows the determination of the stress distribution on the surface of the whole silicon chip. We are able to measure the shear and both main stresses in-plane of the chip surface with a resolution of < 10 MPa. The stress value of the measurement cell can be interrogated subsequently within 16 ms time steps. We used the main potential of this stress measurement chip by replacing the original electronic chip and investigating all production related loads acting on leadframe based QFN products. With the stress measurement chip we investigated wafer thinning as well as typical packaging processes like transfer molding. The measurement of stresses during soldering of QFN parts on printed circuit boards stretches the view towards the consumer product. We investigated application driven questions like the thickness of QFN packages and whether the QFN or chip size determines stresses inside the component

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As the number of applications for flexible assemblies is growing there is also a larger variation of requirements for such packages. Therefore different technologies have been developed for applications from CSP's to smart cards. The scope of the paper is to describe different approaches for packaging using ultra-thin and flexible chips. This includes the assembly processes as well as packaging concepts e.g. CSP's, 3D modules and volumetric integration of passive and active components into modules and substrates

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