1982
DOI: 10.1063/1.93438
|View full text |Cite
|
Sign up to set email alerts
|

Empirical study of the metal-nitride-oxide-semiconductor device characteristics deduced from a microscopic model of memory traps

Abstract: A graded-nitride gate dielectric metal-nitride-oxide-semiconductor (MNOS) memory transistor exhibiting superior device characteristics is presented and analyzed based on a qualitative microscopic model of the memory traps. The model is further reviewed to interpret some generic properties of the MNOS memory transistors including memory window, erase-write speed, and the retention-endurance characteristic features.

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
3
1
1

Citation Types

0
10
0

Year Published

1985
1985
2018
2018

Publication Types

Select...
5
3

Relationship

0
8

Authors

Journals

citations
Cited by 48 publications
(10 citation statements)
references
References 14 publications
0
10
0
Order By: Relevance
“…Creation of N5° centers by a high-temperature postdepo- (1] sition anneaL-Our previous results are summarized in Fig. 4, which shows EPR traces of a-SiN144:H thin films subjected to various conditions: (a) as-deposited, (b) UV illuminated, (c) after annealing at 700°C for 10 mm in N2, and (d) after annealing followed by broad-band UV illumination."…”
Section: Methodsmentioning
confidence: 96%
“…Creation of N5° centers by a high-temperature postdepo- (1] sition anneaL-Our previous results are summarized in Fig. 4, which shows EPR traces of a-SiN144:H thin films subjected to various conditions: (a) as-deposited, (b) UV illuminated, (c) after annealing at 700°C for 10 mm in N2, and (d) after annealing followed by broad-band UV illumination."…”
Section: Methodsmentioning
confidence: 96%
“…The Si 3 N 4 characteristic is simulated by a generic Poole-Frenkel law and the SiO 2 Si characteristic by a Fowler-Nordheim law with a Si/SiO 2 barrier of 2.9 eV. Concerning the SiO 2 SiN characteristic, we considered the two classical explanations reported in the literature, namely, anode hole injection 6 and electron injection from nitride traps 14,22 ͓see Fig. 1͑c͔͒.…”
Section: A Current Continuity Modelmentioning
confidence: 99%
“…4͑a͒, was obtained by setting ϭ3.10 Ϫ15 cm 2 , 35,36 ͑which means E loc ϭ1.1ϫ10 Ϫ3 eV), N st ϭ10 12 /cm 2 , 36,37 and t ϭ3.5 eV. 1,22 It should be noticed that Eq. ͑5͒ does not consider the occupancy factor of the trap, which means that conduction is assumed to be independent of the trap filling process.…”
Section: A Current Continuity Modelmentioning
confidence: 99%
See 1 more Smart Citation
“…In NVM, the memory window, the difference between the programming and erasing voltages, should be set to secure a sufficient margin of read voltage ( V read ) for stable device operation; wider memory windows can be achieved by producing more defect sites to trap more charges. However, shallow traps adversely affect device stability. , Therefore, it is necessary to selectively exclude shallow trap sites to satisfy both a wide memory window and high device stability. In this work, a novel oxide FET-based NVM device without a tunneling oxide is proposed, employing the deep trap interface (DI) as a simple floating gate.…”
Section: Introductionmentioning
confidence: 99%