Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator

Kim, Stephen T.; Shih, Yu-Jen; Mazumdar, Kaushik; Jain, Rachna; Ryan, Joseph F.; Tokunaga, Carlos; Augustine, Charles; Kulkarni, Jaydeep P.; Ravichandran, Krishnan; Tschanz, James; Khellah, Muhammad; De, Vivek

doi:10.1109/jssc.2015.2457920

Cited by 62 publications

(5 citation statements)

References 13 publications

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“…The efficiency of DC-DC converters can reach more than 90% [1,2,3,4,5,6,7,8,9]. However, its large output ripple limits its applications in sensitive electronic load where additional LDO is required to achieve low power noise and ripple [10,11,12,13,14,15,16,17,18,19]. Hybrid methods of switched-mode, switched-capacitor-mode DC-DC, low dropout voltage regulator (LDO) are proposed in recent years [20,21,22,23,24].…”

Section: Introductionmentioning

confidence: 99%

A novel DC-DC converter and LDO cascaded circuit with improved dynamic response and loop stability

Zhou

Min

Luo

2021

IEICE Electron. Express

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Presented is a new type of DC-DC converter and low dropout voltage regulator (LDO) cascaded circuit, which has improved dynamic response and loop stability. In this novel cascaded circuit, the gate voltage of the pass element of the LDO is quantized and compared with a target value to form an error value to finally control the feedback coefficient of the DC-DC converter. Meanwhile, the adjusting speed of this feedback coefficient can be changed dynamically through the gain compensator, which is minimized to obtain the best loop stability when approaching the steady-state and increased to achieve a fast transient response during large dynamic change. The testing results of the prototype designed to verify the feasibility show that the novel cascaded circuit can increase the response speed by 22 times and optimize the voltage ripple by 1.9 times.

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Section: Introductionmentioning

confidence: 99%

A novel DC-DC converter and LDO cascaded circuit with improved dynamic response and loop stability

Zhou

Min

Luo

2021

IEICE Electron. Express

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“…With the growing demands for high performance computations, both the current consumption and the current slew rate of modern microprocessors have dramatically increased [1] . Large and rapid current changes due to load variations incur large power supply voltage droops, resulting in severe performance degradation or even black-outs of the processors [2][3][4] . To mitigate the problem, the DC-DC converters that supply power to the processors should have fast transient responses so that both the magnitude and the duration of the voltage droops are reduced.…”

Section: Introductionmentioning

confidence: 99%

Fast-transient techniques for high-frequency DC–DC converters

Cheng

Tang

et al. 2020

J. Semicond.

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A 30 MHz voltage-mode controlled buck converter with fast transient responses is presented. An improved differential difference amplifier (DDA)-based Type-III compensator is proposed to reduce the settling times of the converter during load transients, and to achieve near-optimal transient responses with simple PWM control only. Moreover, a hybrid scheme using a digital linear regulator with automatic transient detection and seamless loop transition is proposed to further improve the transient responses. By monitoring the output voltage of the compensator instead of the output voltage of the converter, the proposed hybrid scheme can reduce undershoot and overshoot effectively with good noise immunity and without interrupting the PWM loop. The converter was fabricated in a 0.13 μm standard CMOS process using 3.3 V devices. With an input voltage of 3.3 V, the measured peak efficiencies at the output voltages of 2.4, 1.8, and 1.2 V are 90.7%, 88%, and 83.6%, respectively. With a load step of 1.25 A and rise and fall times of 2 ns, the measured 1% settling times were 220 and 230 ns, with undershoot and overshoot with PWM control of 72 and 76 mV, respectively. They were further reduced to 36 and 38 mV by using the proposed hybrid scheme, and 1% settling times were also reduced to 125 ns.

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“…Power management of mobile devices and communication networks have been advancing with the growing number of mobile consumer electronics and Internet of Things (IoT) devices. To improve their power efficiency and battery life, multiple levels of engineering efforts have been conducted from system-level optimization [1][2][3][4] to device-level power management such as dynamic voltage and frequency scaling [5][6][7][8]. Digital systems and system-on-chip devices usually have multiple voltage domains that need to be adjusted reflecting dynamic variations of load conditions.…”

Section: Introductionmentioning

confidence: 99%

An Output Capacitor-Less Low-Dropout Regulator with 0–100 mA Wide Load Current Range

Park

Kang

et al. 2019

Energies

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An output capacitor-less low-dropout (OCL-LDO) regulator with a wide range of load currents is proposed in this study. The structure of the proposed regulator is based on the flipped-voltage-follower LDO regulator. The feedback loop of the proposed regulator consists of two stages. The second stage is turned on or off depending on the variation in the output load current. Hence, the regulator can retain a phase margin at a wide range of load currents. The proposed regulator exhibits a better regulation performance compared to the ones in previous studies. The test chip is fabricated using a 65-nm CMOS process.

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Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator

Cited by 62 publications

References 13 publications

A novel DC-DC converter and LDO cascaded circuit with improved dynamic response and loop stability

A novel DC-DC converter and LDO cascaded circuit with improved dynamic response and loop stability

Fast-transient techniques for high-frequency DC–DC converters

An Output Capacitor-Less Low-Dropout Regulator with 0–100 mA Wide Load Current Range

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