Energy-aware and fault-tolerant custom topology design method for network-on-chips

Kullu, Pinar; Tosun, Suleyman

doi:10.1016/j.nancom.2018.12.001

Cited by 10 publications

(75 citation statements)

References 14 publications

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“…The authors then used the reconfiguration technique to switch between the routers in the topology in the second step. The authors of [10] described a fault-tolerant ASNoC created by modifying the ring topology with GA. They modeled the base topology as a Ring and reduced the distance between the two routers by incorporating spare links into the topology.…”

Section: Literature Surveymentioning

confidence: 99%

“…For the experiment, the link length and width are 1 mm and 1 µm, respectively. According to the approach [32], the MTTF of a link is determined by the communication traffic (e) FTTG generated using our approach for a specific link fault (f) FTTG generated using our approach for any link fault FIGURE 1: FTTGs generated for MP3Encoder's ACG using the approaches [5], [9], [10], and our approach for a specific link and any link fault that passes through it. If a link in the topology has a high communication bandwidth, it has a lower MTTF value, and vice versa.…”

Section: T T Fmentioning

confidence: 99%

“…However, the high average hop count between the routers in the Ring topology has a negative impact. Similarly, in one of their recent works [10], the average hop count in the Ring topology was improved by adding a link between the topology's routers. This new link will provide two alternate routing paths for data from the source core to the destination core.…”

Section: Introductionmentioning

confidence: 99%

“…This new link will provide two alternate routing paths for data from the source core to the destination core. However, in the event of a single link failure, the faulttolerant ASNoC designs generated by the approaches [5], [9], [10] resulted in an excess hop count. The main reason is that they used the Ring topology as the foundation for the fault-tolerant ASNoC design.…”

Section: Introductionmentioning

confidence: 99%

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Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA

et al. 2021

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Application-Specific Networks-on-Chips (ASNoCs) are suitable communication platforms for meeting current application requirements. Interconnection links are the primary components involved in communication between the cores of an ASNoC design. The integration density in ASNoC increases with continuous scaling down of the transistor size. Excessive integration density in ASNoC can result in the formation of thermal hotspots, which can cause a system to fail permanently. As a result, faulttolerant techniques are required to address the permanent faults in interconnection links of an ASNoC design. By taking into account link faults in the topology, this paper introduces a fault-tolerant applicationspecific topology-based NoC design and its prototype on an FPGA. To place spare links in the ASNoC topology, a meta-heuristic algorithm based on Particle Swarm Optimization (PSO) is proposed. By taking link faults into account in ASNoC design, we also propose an application mapping heuristic and a tablebased fault-tolerant routing algorithm. Experiments are carried out for a specific link and any link fault in fault-tolerant topologies generated by our approach and approaches reported in the literature. For the experimentation, we used the multi-media applications Picture-in-Picture (PiP), Moving Pictures Expert Group (MPEG) -4, MP3Encoder, and Video Object Plane Decoder (VOPD). Experiments are run on software and hardware platforms. The static performance metric communication cost and the dynamic performance metrics network latency, throughput, and router power consumption are examined using software platform. In the hardware platform, the Field Programmable Gate Array (FPGA) is used to validate proposed fault-tolerant topologies and analyze performance metrics such as application runtime, resource utilization, and power consumption. The results are compared with the existing approaches, specifically Ring topology and its modified versions on both software and hardware platforms. The experimental results obtained from software and hardware platforms for a specific link and any link fault show significant improvements in performance metrics using our approach when compared with the related works in the literature.

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Section: Literature Surveymentioning

confidence: 99%

Section: T T Fmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA

et al. 2021

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“…In recent years, the number of studies on irregular topologies has increased considerably, as it offers better optimisation space for several parameters such as performance, energy, and area [2, 11–13, 21–27]. While some of these studies propose methods that generate fault‐tolerant topologies providing more than one path between each communicating pair of nodes [2, 21–23, 26, 27], some of them focus on other criteria by ignoring fault tolerance [11–13, 24, 25]. The authors of [11] propose two different methods to generate irregular topologies that meet the requirements of the given application.…”

Section: Related Workmentioning

confidence: 99%

Mapping application‐specific topology to mesh topology with reconfigurable switches

Kullu¹,

Ar²,

Tosun³

et al. 2019

IET Computers & Digital Techniques

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When designing a Network-on-Chip (NoC) architecture, designers must consider various criteria such as bandwidth, performance, energy consumption, cost, re-usability, and fault tolerance. In most of the design efforts, it is very difficult to meet all these interacting constraints and objectives at the same time. Some of these parameters can be optimised and met easily by regular NoC topologies due to their re-usability and fault-tolerance capabilities. On the other hand, other parameters such as energy consumption, performance, and chip area can be better optimised in irregular NoC topologies. In this work, the authors present a novel two-step method that combines the advantages of regular and irregular NoC topologies. In the first step, the authors' method generates an energy and area optimised irregular topology for the given application by using a genetic algorithm. The generated topology uses the least amount of routers and links to minimise the area and energy; thus, it offers only one routing path between communicating nodes. Therefore, it does not fault tolerant. In the second step, their method maps the generated irregular topology to a reconfigurable mesh topology to make it fault tolerant. The detailed simulation results show the superiority of the proposed method over the existing work on several multimedia benchmarks.

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Optimizing Network-on-Chip using metaheuristic algorithms: A comprehensive survey

Masdari,

Qasem,

Pai

2023

Microprocessors and Microsystems

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Energy-aware and fault-tolerant custom topology design method for network-on-chips

Cited by 10 publications

References 14 publications

Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA

Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA

Mapping application‐specific topology to mesh topology with reconfigurable switches

Optimizing Network-on-Chip using metaheuristic algorithms: A comprehensive survey

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