Energy considerations in multichip-module based multiprocessors

Burr, James; Peterson, A.

doi:10.1109/iccd.1991.139981

Cited by 23 publications

(14 citation statements)

References 9 publications

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“…By definition, the unity-gain point is found by setting the derivative of (18) with respect to to 1, thereby yielding (19) which can be substituted into (18) to evaluate (20) The unity-gain point can be found by swapping pMOS/nMOS transistors and repeating the above procedure, which leads to (21) (22) From (20) and (22), the deviation of output-referred coordinates from the ideal output value and are independent of the transistor strength and supply voltage. Indeed, they depend only on the adopted technology through parameter .…”

Section: A Evaluation Of the Unity-gain Pointsmentioning

confidence: 99%

“…In [19], the inverse DC characteristics is evaluated again under the unrealistic assumption of perfectly balanced pMOS/nMOS transistors, and does not provide closed-form expression of the main DC parameters. The qualitative analysis in [20] and [21] and the numerical analysis in [22] and [23] do not lead to closed-form expressions of DC parameters.…”

Section: Introductionmentioning

confidence: 99%

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Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis

Alioto

2010

IEEE Trans. Circuits Syst. I

154

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In this paper, the DC behavior of subthreshold CMOS logic is analyzed in a closed form for the first time in the literature. To this aim, simplified large-signal and small-signal models of MOS transistors in subthreshold region are first developed. After replacing transistors with these equivalent models, analysis of the main DC parameters of CMOS logic gates is presented. In particular, the change in the DC characteristics shape due to operation at ultra-low voltages is analyzed in detail, evaluating analytically the degradation in the logic swing, the symmetry and the steepness of the transition region, as well as the change in the unity-gain points position. The resulting expressions permit to gain an insight into the basic dependence of DC behavior on design and device parameters. The noise margin is explicitly evaluated and modeled with a very simple expression. Interestingly, analysis shows that the noise margin deviates from the ideal half-swing value by an amount that linearly depends on the logarithm of the -ratio. Analysis permits to evaluate the minimum supply voltage that ensures correct operation of CMOS logic (i.e., positive noise margin). Previously proposed rule of thumbs to evaluate minimum voltage are also theoretically justified. Moreover, the impact of pMOS/nMOS unbalancing on DC characteristics is analyzed from a design perspective. Considerations on the impact of process/voltage/temperature variations are also introduced. Results are validated through extensive simulations in a 65-nm CMOS technology.Index Terms-DC behavior, noise immunity, subthreshold CMOS logic, ultra-low power, VLSI.

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Section: A Evaluation Of the Unity-gain Pointsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis

Alioto

2010

IEEE Trans. Circuits Syst. I

154

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“…It is remarkable that, despite the reduction in supply voltage at small feature sizes, logic performance continues to improve. Several authors have emphasized the improvement in speed that we can make available by reducing threshold and power-supply voltages [12,[31][32][33].…”

Section: Supplymentioning

confidence: 99%

Scaling of MOS technology to submicrometer feature sizes

Mead

1994

Analog Integr Circ Sig Process

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Industries based on MOS technology now play a prominent role in t he developed and the developing world. j\fore importantly, MOS techn ology drives a large proportion of innovation in many technologies . It is likely th at the course of technological development depends more on the capability of MOS technology than on any other technical factor . T herefore, it is worthwhile investigating the na.ture and limits of future improvements to MOS fabrication. The key to improved MOS technology is r eduction in feature size. Reduction in feature size, and the attendant changes in device behaviour, will shape the nature of effective uses of the technology at t he system level. This paper reviews recent, and historical, data on feature scaling and device behavior, and attempts to predict the limits to this scaling. We conclude wi th som e remarks on the system-level implications of fea.ture size as the minimum size approach es physical limits. IntroductionIt is always difficult . to nredict the future; few attemp ts to do so have met with resounding su ccess. One remarkable example of successful prediction is the exponential increase in complexity of integrated circuits, first noted by Gordon E . !vioor e. As we contemplate the ongoing evolution of this great technology, many questions arise: Can the trend continue? Will single-chip systems attain levels of complexity that render present system archit ectures unworkable [lj? vVill digital t.echniques completely replace analog methods [2]"7 The answers to these questions depend critically on the properties of the individual transistor s that provide the essential active functions, without which no interesting system beh avior is possible. Integrated-circuit density is increased by a reduction in the size of elementary feat.ures of the underlying structures; therefore, any discussion of the capabilities of future technologies must rely on an understanding of how the properties of transistors evolve as the transistor s' dimensions are made smaller.Elsewhere [3], we described the factors that limit how small an MOS transistor *Reproduced from Journal of VLSI Signal P rocessing, 8 , 9-25 (1994) Kluwer Academic Publishers, Boston. ~fanufacture d in The Netherlands.

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“…The other issue related to SO1 based circuits is the design of Vrr+ As the power supply scales, Vrrr has to scale to maintain fast switching. But, the minimum of V,, is mainly limited by circuit functionality and noise margin [5]. Basically, V, is given by Zog(I,,&,~)xS.…”

Section: Speed: Parasitic Capacitances and Vmentioning

confidence: 99%