Energy efficient streaming applications with guaranteed throughput on MPSoCs

Zhu, Jun; Sander, Ingo; Jantsch, Axel

doi:10.1145/1450058.1450075

Cited by 18 publications

(21 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Synchronous dataflow (SDF) and cyclo-static dataflow (CSDF) are also known to be powerful modeling tools for static compile-time scheduling onto single and multicore processors [27], [28]. scheduling solutions based on data flow models are designed for hard real-time tasks.…”

Section: Related Workmentioning

confidence: 99%

Online Energy-Efficient Task-Graph Scheduling for Multicore Platforms

Kanoun

Mastronarde

Atienza

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

Abstract-Numerous directed acyclic graph (DAG) schedulers have been developed to improve the energy efficiency of various multicore platforms. However, these schedulers make a priori assumptions about the relationship between the task dependencies, and they are unable to adapt online to the characteristics of each application without offline profiling data. Therefore, we propose a novel energy-efficient online scheduling solution for the general DAG model to address the two aforementioned problems. Our proposed scheduler is able to adapt at run-time to the characteristics of each application by making smart foresighted decisions, which take into account the impact of current scheduling decisions on the present and future deadline miss rates and energy efficiency. Moreover, our scheduler is able to efficiently handle execution with very limited resources by avoiding scheduling tasks that are expected to miss their deadlines and do not have an impact on future deadlines. We validate our approach against state-of-the-art solutions. In our first set of experiments, our results with the H.264 video decoder demonstrate that the proposed low-complexity solution for the general DAG model reduces the energy consumption by up to 15% compared to an existing sophisticated and complex scheduler that was specifically built for the H.264 video decoder application. In our second set of experiments, our results with different configurations of synthetic DAGs demonstrate that our proposed solution is able to reduce the energy consumption by up to 55% and the deadline miss rates by up to 99% compared to a second existing scheduling solution. Finally, we show that our DAG flow manager and scheduler have low complexities on a real mobile platform and we show that our solution is resilient to workload prediction errors by using different estimator accuracies.

show abstract

Section: Related Workmentioning

confidence: 99%

Online Energy-Efficient Task-Graph Scheduling for Multicore Platforms

Kanoun

Mastronarde

Atienza

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…to deal with memory dimensioning [9], a synchronous variant [10] based on periodic abstract clocks, has been defined with N -bounded channels for synchronizability analysis between processes.…”

Section: Related Workmentioning

confidence: 99%

“…SDFs are not explicitly clocked, which is a limitation for expressing multiclock behaviors in combined software, hardware and environment specifications. For this reason in [9], authors consider a translation from SDF models to synchronous models.…”

Section: Related Workmentioning

confidence: 99%

Design of streaming applications on MPSoCs using abstract clocks

Gamatie

2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

View full text Add to dashboard Cite

This paper presents a cost-effective and formal approach to model and analyze streaming applications on multiprocessor systems-on-chip (MPSoCs). This approach enables to address time requirements, mapping of applications on MPSoCs and system behavior correctness by using abstract clocks of synchronous languages. Compared to usual prototyping and simulation techniques, it is very fast and favors correctness-byconstruction. No coding is needed to run and analyze a system, which avoids tedious debugging efforts. It is an ideal complement to existing techniques to deal with large system design spaces.

show abstract

“…Here we only consider those allowing inter-task dependencies, as we also do. [15]- [20] consider applications described as directed acyclic task graphs (DAG), [9], [21] tackle the more general case of cyclic dataflow task graphs, and [22] models application using network calculus, expressing dependencies implicitly, via arrival curves. [15] combines DVFS and adaptive body biasing in heterogeneous platforms; [16] iteratively distributes slack over the DAG's nodes.…”

Section: Related Workmentioning

confidence: 99%

“…[9]'s RTOS is closest to our approach, but is not composable, nor implemented on FPGA. [21] uses a similar dataflow model and streaming applications as in [9], exploring the design space for memory size and processor voltage frequency levels, while meeting a throughput constraint, but without processor sharing. [22] proposes a DVFS strategy in two phases: off-line worstcase bounds that are conservatively improved at run time.…”

Section: Related Workmentioning

confidence: 99%

Composable Dynamic Voltage and Frequency Scaling and Power Management for Dataflow Applications

Goossens

She

Milutinovic

et al. 2010

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

View full text Add to dashboard Cite

Abstract-Composability means that the behaviour of an application, including its timing, is not affected by the absence or presence of other applications. It is required to be able to design, test, and verify applications independently. In this paper we define composable dynamic voltage and frequency scaling (DVFS) hardware, and composable power management. We ensure that the functional and temporal behaviours of an application are not affected by other applications, even when they are power managed.For dataflow applications with worst-case execution times per task, our power management is also predictable, i.e. guarantees end-to-end real-time requirements, even when the application is mapped on multiple processors that are power managed independently. Our method can be used with various DVFS architectures, such as on-chip and off-chip VF regulators.Our FPGA implementation models a system with multiple tiles, each containing a processor with local memory running a realtime operating system (RTOS) and power management. Tiles are interconnected by a network on chip, and communicate using shared memories. Experiments indicate energy savings of 68% w.r.t. no power management, and 40% w.r.t. power gating only. We also demonstrate composability and predictability on the platform in the presence of power management. I. INTRODUCTION Low energy consumption is important for systems on chip (SOC). Dynamic voltage and frequency scaling (DVFS) is oftenused to trade a linear processor slowdown for a potentially quadratic decrease in energy consumption. This trade-off has been exhaustively addressed for single processors, and for multi-processor SOCs [1], [2]. We propose an architecture that uses existing DVFS hardware to build composable and predictable SOCs running multiple applications.To deal with the complexity of system design and verification, the concept of composability has been advocated [3]-[6] and practised [7]. Behaviours of different applications are independent, to be able to develop, test, verify, and execute applications in isolation before they are integrated to a system. A composable SOC then ensures that applications already integrated do not affect the newly added application, and vice versa.Embedded systems contain a mix of best-effort applications, and those that have (hard or soft) real-time requirements, such as radio pipes, and video and audio decoding. Predictability, or timeliness, is required to guarantee that each application meets its deadlines, while composability ensures that multiple

show abstract

Energy efficient streaming applications with guaranteed throughput on MPSoCs

Cited by 18 publications

References 18 publications

Online Energy-Efficient Task-Graph Scheduling for Multicore Platforms

Online Energy-Efficient Task-Graph Scheduling for Multicore Platforms

Design of streaming applications on MPSoCs using abstract clocks

Composable Dynamic Voltage and Frequency Scaling and Power Management for Dataflow Applications

Contact Info

Product

Resources

About