Energy-Efficient Wide-Range Voltage Level Shifters Reaching 4.2 fJ/Transition

Lotfi, Reza; Saberi, Mehdi; Hosseini, Seyed Rasool; Mehr, Seyed Amir Reza Ahmadi; Staszewski, Robert Bogdan

doi:10.1109/lssc.2018.2810606

Cited by 58 publications

(11 citation statements)

References 18 publications

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“…The minimum convertible voltage of the proposed level shifter and its energy per transition (at 1 MHz) are the lowest among the circuits in Table II. A variant of LS in [20] achieves an extremely low energy per transition of 4.2 fJ at the cost of higher minimum V ddL (120 mV). The designed LS has second shortest delay after [19] in Table II, while at 0.2 V it has the shortest reported delay among the listed LSs.…”

Section: Discussionmentioning

confidence: 99%

An Ultra-Low Voltage and Low-Energy Level Shifter in 28-nm UTBB-FDSOI

Vatanjou

Ytterdal

Aunet

2019

IEEE Trans. Circuits Syst. II

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A low-power level shifter capable of up-converting sub-50 mV input voltages to 1 V has been implemented in a 28 nm FDSOI technology. Diode connected transistors and a single-NWELL layout strategy have been used along with poly and back-gate biasing techniques to achieve an adequate balance between the drive strength of the pull-up and the pull-down networks. Measurements showed that the lowest input voltage levels, which could be upconverted by the 10 chip samples, varied from 39 mV to 52 mV. Half of the samples could upconvert from 39 mV to 1 V. The simulated energy consumption of the level shifter was 5.2 fJ for an up-conversion from 0.2 V to 1 V and 1 MHz operating frequency.

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Section: Discussionmentioning

confidence: 99%

An Ultra-Low Voltage and Low-Energy Level Shifter in 28-nm UTBB-FDSOI

Vatanjou

Ytterdal

Aunet

2019

IEEE Trans. Circuits Syst. II

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“…The main challenge is to raise a supplied clock to the output of the start-up charge pump is Vo2 cannot directly connect in series with two clocks (ɸM, ɸM ). Therefore, the level shifter [7] is used to level shift the amplitude of the clock from VPV, powered from the PV cell, is pulled up to the higher amplitude (Vo2). To achieve that, one output of the previous start-up circuits will act as the VDDH of the level shifter, and thus original amplitude of the clock will raise to new VDDH value.…”

Section: Level-shifting Clockmentioning

confidence: 99%

“…This secondary output enables the idea of supplying high voltage clock to the main charge pump, 3-stages cross-coupled circuit [6]. The level shifter proposed in [7] is used to increase the amplitude of the clock signal to the output of the start-up charge pump to gather more VGR at the second main charge pump output.…”

Section: Introductionmentioning

confidence: 99%

Energy-Efficient Start-up Power Management for Batteryless Biomedical Implant Devices

Htet

Zhao

Ghannam

et al. 2018

2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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This paper presents a solar energy harvesting power management using the high-efficiency switchedcapacitor DC-DC converter for biomedical implant applications. By employing an on-chip start-up circuit with parallel connected Photovoltaic (PV) cells, a small efficiency improvement can be obtained when compared with the traditional stacked photodiode methodology to boost the harvested voltage while preserving a single-chip solution. The PV cells have been optimised in the PC1D software and the optimal parameters modelled in the Cadence environment. A cross-coupled circuit with level shifter loop is also proposed to improve the overall step up voltage output and hybrid converter increases the start-up speed by 23.5%. The proposed system is implemented in a standard 0.18-μm CMOS technology. Simulation results show that the 4-phase start-up and crosscoupled with level-shifter can achieve a maximum efficiency of 60%.

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“…Multiple voltage domains are also found in fixed supply applications. An SoC may use diverse supply voltages, achieving different power consumption modes (e.g., sleep mode) 6‐10 . As Figure 2 describes, these power domains are usually isolated, demanding blocks capable of ensuring proper voltage levels for control signals between them.…”

Section: Introductionmentioning

confidence: 99%

“…Although some LSs using only thin devices have been previously reported, 1,6 their application demands lower supply voltages than the nominal voltage for thin gate oxide devices. For instance, in Lotfi et al 6 V DDL is 0.35 V and V DDH is the nominal voltage of the technology node at 40 nm, 1.1 V. Reported architectures are not appropriate solutions for the problem described, where V DDL and V DDH (1.8 to 3.3 V) become larger and can cause problems with device maximum voltage ratings.…”

Section: Introductionmentioning

confidence: 99%

A single gate oxide level shifter for denser digital domain integration in multiple‐supply‐voltage applications

Cuevas

Gomez

Roa

2020

Circuit Theory & Apps

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Summary Modern system‐on‐chip (SoC) applications usually employ multiple voltage domains to save power consumption according to the required circuit performance. Typical multivoltage approaches use level shifters (LSs) to establish communication among voltage domains. The use of commercial standard‐cell and multiple gate oxide MOS LSs implies a nonoptimal place‐and‐route process. Here, we introduce a single gate oxide level shifter (SGOLS) that enables full integration into low‐voltage domains. We tested the proposed idea using a commercial digital‐flow tool for a two‐domain SoC integration, achieving an enhancement in the total integration area occupied by LSs of 54% regarding the conventional LS approaches. The proposed SGOLS was implemented in both 65‐ and 180‐nm CMOS nodes, handling voltage differences between the nominal and I/O domain supplies by using just single gate oxide devices. We validated the circuit performance through process, voltage, and temperature (PVT) variations for wide frequency and supply voltage ranges, disclosing an energy‐per‐transition of 416 fJ@180 nm and 93 fJ@65 nm. The introduced LS extends the integration of multiple voltage domains into denser SoCs.

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Energy-Efficient Wide-Range Voltage Level Shifters Reaching 4.2 fJ/Transition

Cited by 58 publications

References 18 publications

An Ultra-Low Voltage and Low-Energy Level Shifter in 28-nm UTBB-FDSOI

An Ultra-Low Voltage and Low-Energy Level Shifter in 28-nm UTBB-FDSOI

Energy-Efficient Start-up Power Management for Batteryless Biomedical Implant Devices

A single gate oxide level shifter for denser digital domain integration in multiple‐supply‐voltage applications

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