Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling

Nunez-Yanez, Jose; Hosseinabady, Mohammad; Beldachi, Arash Farhadi

doi:10.1109/tc.2015.2435771

Cited by 37 publications

(30 citation statements)

References 17 publications

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“…The user design is the S2NN in this paper and the AXI-PCAP port can be used to load different network configurations on the fly without altering the DFS and DVS logic and status. As shown in our previous work on DVFS [Nunez-Yanez et al 2016] this DVFS-enable architecture has a logic overhead of around 5% which has a very small impact in power at the same voltage and frequency because in the FPGA device most of the power is not due to the additional configured logic cells but due to leakage and clock networks.…”

Section: Energy Efficiency and Proportionalitymentioning

confidence: 92%

“…Adaptation of voltage and frequencies is achieved using the voltage regulators and mixed mode frequency generation using a power adaptive architecture presented in Fig.10. This architecture is part of our previous work [Nunez-Yanez et al 2016] and the interested reader is refer to that paper for more information. It consist of a DVS (Dynamic Voltage Scaling) unit that uses the PMBUS present in the device to adjust voltage levels and measure current and a DFS (Dynamic Frequency Scaler) that uses the MMCM (Mixed Mode Clock Managers) to synthesis new frequencies on the fly.…”

Section: Energy Efficiency and Proportionalitymentioning

confidence: 99%

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Energy proportional streaming spiking neural network in a reconfigurable system

Sanchez

Nunez-Yanez²

2017

Microprocessors and Microsystems

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This paper presents a high-performance architecture for spiking neural networks that optimizes data precision and streaming of configuration data stored in main memory. The neural network is based on the Izhikevich model and mapped to a CPU-FPGA hybrid device using a high-level synthesis flow. The active area of the network is configurable and this feature is used to create an energy proportional system. Voltage and frequency scaling are applied to the processing hardware and memory system to deliver enough processing and memory bandwidth to maintain real-time performance at minimum power and energy levels. The experiments show that the application of voltage and frequency scaling to DDR memory and programmable logic can reduce its energy requirements by up to 77% and 76% respectively. The performance evaluation show that the solution is superior to competing high-performance hardware, while voltage and frequency scaling reduces overall energy requirements to less than 2% of a software-only implementation at the same level of performance. Index terms: Hardware → Integrated circuits → Reconfigurable logic and FPGAs → Hardware accelerators, Hardware → Integrated circuits → Reconfigurable logic and FPGAs → Reconfigurable logic applications

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Section: Energy Efficiency and Proportionalitymentioning

confidence: 92%

Section: Energy Efficiency and Proportionalitymentioning

confidence: 99%

Energy proportional streaming spiking neural network in a reconfigurable system

Sanchez

Nunez-Yanez²

2017

Microprocessors and Microsystems

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“…Voltage scaling is also used in FPGA based design of cyclic redundancy check [6], flip-flop [7] and Wi-Fi Ah Channel enable ALU [8]. [9] Investigates the possibility of reductions possible in commercially available FPGAs configured to support voltage, frequency and logic scalability combined with power gating. Voltage and frequency scaling is based on in-situ detectors that allow the device to detect valid working voltage and frequency pairs at run-time while logic scalability is achieved with partial dynamic reconfiguration [9].…”

Section: Related Workmentioning

confidence: 99%

Scaling of Supply Voltage in Design of Energy Saver FIR Filter on 28nm FPGA

Pandey¹,

Jain²,

Yadav³

et al. 2017

IJCA

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“…mobile, battery supplied and hand-held devices) [3].As a consequence, energy efficiency is gradually becoming one fundamental constraint and requisite for embedded systems design, often requiring the adoption of new technologies [4,5] and micro-architecture design approaches [6][7][8][9][10].This special issue (SI) of the EURASIP Journal on Embedded Systems (Springer) entitled "Energy Efficient Architectures for Embedded Systems" is mainly focused on new design and development trends of energy efficient processing architectures for embedded systems. The collection of papers presented here emphasizes several aspects of this research domain, including not only architectures and specific design methods but also more technological aspects related to micro-architecture design, memory hierarchies, communication mechanisms and tools/algorithms for energy/power management and control.…”

mentioning

confidence: 99%

“…As a consequence, energy efficiency is gradually becoming one fundamental constraint and requisite for embedded systems design, often requiring the adoption of new technologies [4,5] and micro-architecture design approaches [6][7][8][9][10].…”

mentioning

confidence: 99%

Editorial to special issue on energy efficient architectures for embedded systems

Roma

Nunez-Yanez

2016

J Embedded Systems

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In the last decades, a significant boost in embedded computing systems performance has been observed in several different domains, mostly due to technology scaling and to the ever increasing exploitation of parallel processing architectures [1].However, although conventional approaches relying on homogeneous/heterogeneous chip-multiprocessor aggregates already allow achieving a significant performance level [2], important compromises are necessary in order to cope with the strict energy efficiency requirements present in many embedded application domains (e.g. mobile, battery supplied and hand-held devices) [3].As a consequence, energy efficiency is gradually becoming one fundamental constraint and requisite for embedded systems design, often requiring the adoption of new technologies [4,5] and micro-architecture design approaches [6][7][8][9][10].This special issue (SI) of the EURASIP Journal on Embedded Systems (Springer) entitled "Energy Efficient Architectures for Embedded Systems" is mainly focused on new design and development trends of energy efficient processing architectures for embedded systems. The collection of papers presented here emphasizes several aspects of this research domain, including not only architectures and specific design methods but also more technological aspects related to micro-architecture design, memory hierarchies, communication mechanisms and tools/algorithms for energy/power management and control.The call for papers resulted in nine manuscript submissions. For each submission, at least two reviewers examined its quality, together with the guest editors and the editor-in-chief. Finally, four papers were selected for publication that cover the following three prominent topics in embedded system design: computer microarchitectures for energy efficiency, energy/power models *Correspondence: nuno.roma@inesc-id.pt 1 INESC-ID, Instituto Superior Técnico, Universidade de Lisboa, Rua Alves Redol, 9, 1000-029 Lisboa, Portugal Full list of author information is available at the end of the article and management strategies, and energy-efficient memory hierarchy subsystems.The paper entitled "A hybrid fixed-function and microprocessor solution for high-throughput broad-phase collision detection", by Muiris Woulfe and Michael Manzke, presents a hybrid processing system spanning a fixedfunction microarchitecture and a general-purpose microprocessor, designed to increase the throughput and reduce the power dissipation of collision detection relative to what can be achieved using CPUs or GPUs alone. The primary component is one of two novel microarchitectures designed to perform the principal elements of broad-phase collision detection. Both microarchitectures consist of processing pipelines comprising a plurality of memories, which rearrange the input into a format that maximizes parallelism and bandwidth. The two microarchitectures are combined with the remainder of the system through an original method for sharing data between a ray tracer and the collision-detection microarchitectures to m...

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Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling

Cited by 37 publications

References 17 publications

Energy proportional streaming spiking neural network in a reconfigurable system

Energy proportional streaming spiking neural network in a reconfigurable system

Scaling of Supply Voltage in Design of Energy Saver FIR Filter on 28nm FPGA

Editorial to special issue on energy efficient architectures for embedded systems

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