ESD Protection Design With Lateral DMOS Transistor in 40-V BCD Technology

Wang, Chang-Tzu; Ker, Ming‐Dou

doi:10.1109/ted.2010.2079530

Cited by 36 publications

(13 citation statements)

References 11 publications

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“…Additionally, the whole-chip ESD protection design has been proposed to suggest where the chip should be protected to reduce the ESD risk [18]. The protect method is divided into two types-the first is to design ESD protection circuits, which protect chips by using the gate-couple technique [19,20] and the substrate-trigger technique [20,21]; the second is to design ESD protection devices, which use silicon controlled rectifier (SCR) [22,23], Grounded-gate nMOS (GGnMOS) [24], stacked field-oxide device (FOD) [25], and diodes [26] to protect a chip. The current crowding effect can often reduce the reliability level of UHV LDMOS [27][28][29].…”

Section: Introductionmentioning

confidence: 99%

Electrostatic-Discharge-Immunity Impacts in 300 V nLDMOS by Comprehensive Drift-Region Engineering

2019

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Electrostatic discharge (ESD) events are the main factors impacting the reliability of Integrated circuits (ICs); therefore, the ESD immunity level of these ICs is an important index. This paper focuses on comprehensive drift-region engineering for ultra-high-voltage (UHV) circular n-channel lateral diffusion metal-oxide-semiconductor transistor (nLDMOS) devices used to investigate impacts on ESD ability. Under the condition of fixed layout area, there are four kinds of modulation in the drift region. First, by floating a polysilicon stripe above the drift region, the breakdown voltage and secondary breakdown current of this modulation can be increased. Second, adjusting the width of the field-oxide layer in the drift region when the width of the field-oxide layer is 5.8 μm will result in the minimum breakdown voltage (105 V) but the best secondary breakdown current (6.84 A). Third, by adjusting the discrete unit cell and its spacing, the corresponding improved trigger voltage, holding voltage, and secondary breakdown current can be obtained. According to the experimental results, the holding voltage of all devices under test (DUTs) is greater than that of the reference group, so the discrete HV N-Well (HVNW) layer can effectively improve its latch-up immunity. Finally, by embedding different P-Well lengths, the findings suggest that when the embedded P-Well length is 9 μm, it will have the highest ESD ability and latch-up immunity.

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Section: Introductionmentioning

confidence: 99%

Electrostatic-Discharge-Immunity Impacts in 300 V nLDMOS by Comprehensive Drift-Region Engineering

2019

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“…Therefore researchers have sought for other approaches to solve this problem. The gate-driven, substrate-triggered techniques are proposed to overcome non-uniform current distribution and ensure a strong robustness [10][11][12][13]. Chen first explained the operation principles of those techniques by energy-band diagrams [10].…”

Section: Introductionmentioning

confidence: 99%

“…Chen first explained the operation principles of those techniques by energy‐band diagrams [10]. Chen and Wang modified the finger‐type nLDMOS to square and octagonal ones, and P + trigger regions are reserved at four corners to absorb the trigger current provided by an extra triggering circuit [12, 13]. Thus, on one hand, the proper trigger current need to be carefully considered according to Chen and Ker [10], on the other hand, the ESD detecting and triggering circuits will occupy extra chip area in those solutions.…”

Section: Introductionmentioning

confidence: 99%

Robust lateral double‐diffused MOS with interleaved bulk and source for high‐voltage electrostatic discharge protection

Wang

Jin

Liu

2015

IET Power Electronics

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A device with bulk and source interleaved dotting is fabricated in a 0.5-µm 24 V CDMOS process, and the root cause of why it improves the multi-finger high-voltage lateral double-diffused MOS (LDMOS)'s electrostatic discharge (ESD) robustness is detected by Atlas three-dimensional device simulation and transmission line pulse system. Such device structure obtains strong ESD robustness by enlarging the intrinsic base resistance without increasing device area and sacrificing any ESD performance of nLDMOS. The measurement results demonstrated that, compared with traditional gate-grounded nLDMOS (GG-nLDMOS) with a total length of 400 μm, the proposed device can effectively raise the secondary breakdown current (I t2) from 2.43 A up to 5.55 A, and enhance the ESD current discharge efficiency from 0.29 to 0.70 mA/μm 2 .

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“…Lateral double-diffused metal-oxide-semiconductor field effect transistors (LDMOSFETs) have been attracting a great deal of attention in smart power integrated circuit applications (Kashyap, Mantooth, Vo, & Mojarradi, 2010;Kim, Fossum, & Williams, 1991;Mitros et al, 2001;Wang & Ker, 2010). In recent years, thin-film silicon-on-insulator LDMOS (TF SOI LDMOS) has gained importance due to its possible integration with low-power CMOS devices and heterogeneous microsystems (Bawedin, Renaux, & Flandre, 2004;Kumar & Sithanandam, 2010).…”

Section: Introductionmentioning

confidence: 99%

Thin-film LDMOS on partial SOI with improved breakdown voltage and suppressed kink effect

Wang

Chang

et al. 2013

International Journal of Electronics

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Thin-film (TF) lateral double-diffused metal-oxide-semiconductor field effect transistor (LDMOSFET or LDMOS) of small dimensions on partial silicon-on-insulator (PSOI) with improved breakdown voltage and suppressed kink effect is introduced and studied. The silicon window and field plate can modulate the surface electric field of silicon film and, thus, their design parameters can be adjusted to achieve optimal breakdown voltage. Moreover, the silicon window can also provide a conduction path from the thin silicon film to the substrate and prevent hole accumulation in the floating body of silicon-on-insulator (SOI) devices, which can consequently suppress the kink effect. Effects of the device parameters (e.g. location of the field plate, location of silicon window, and doping concentrations of the drift region, silicon window and substrate) that control the performance of TF PSOI LDMOS are carefully studied. Compared with the conventional TF SOI LDMOS of small dimensions, the simulation results show that this proposed TF PSOI LDMOS exhibits approximately 100% improvement on the breakdown voltage and entirely eliminates the kink effect.

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ESD Protection Design With Lateral DMOS Transistor in 40-V BCD Technology

Cited by 36 publications

References 11 publications

Electrostatic-Discharge-Immunity Impacts in 300 V nLDMOS by Comprehensive Drift-Region Engineering

Electrostatic-Discharge-Immunity Impacts in 300 V nLDMOS by Comprehensive Drift-Region Engineering

Robust lateral double‐diffused MOS with interleaved bulk and source for high‐voltage electrostatic discharge protection

Thin-film LDMOS on partial SOI with improved breakdown voltage and suppressed kink effect

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