ESD protection structure with reduced capacitance and overshoot voltage for high speed interface applications

Dong, Aihua; Salcedo, Javier A.; Parthasarathy, S.; Zhou, Yuanzhong; Luo, Sirui; Hajjar, Jean-Jacques; Liou, Juin J.

doi:10.1016/j.microrel.2017.03.014

Cited by 10 publications

(1 citation statement)

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“…Thus, some modified SCR devices and trigger-assist SCR devices have been invented to reduce the trigger voltage of SCR, such as the modified lateral SCR (MLSCR) [3], the low-voltage triggering SCR (LVTSCR) [4,5], the GGNMOS-triggered SCR [6] and the diode chain triggering SCR (DTSCR) [7]. Furthermore, the direct-connected SCR (DCSCR) has been proposed to significantly reduce the trigger voltage to a level that is as low as twice of one diode's turn-on voltage [8][9][10][11][12][13].…”

Section: Introductionmentioning

confidence: 99%

Area-Efficient Embedded Resistor-Triggered SCR with High ESD Robustness

Hou

Yang

et al. 2019

Electronics

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The trigger voltage of the direct-connected silicon-controlled rectifier (DCSCR) was effectively reduced for electrostatic discharge (ESD) protection. However, a deep NWELL (DNW) is required to isolate PWELL from P-type substrate (PSUB) in DCSCR, which wastes part of the layout area. An area-efficient embedded resistor-triggered silicon-controlled rectifier (ERTSCR) is proposed in this paper. As verified in a 0.3-μm CMOS process, the proposed ERTSCR exhibits lower triggering voltage due to series diode chains and embedded deep n-well resistor in the trigger path. Additionally, the proposed ERTSCR has a failure current of more than 5 A and a corresponding HBM ESD robustness of more than 8 KV. Furthermore, compared with the traditional DCSCR, to sustain the same ESD protection capability, the proposed ERTSCR will consume 10% less silicon area by fully utilizing the lateral dimension in the deep n-well extension region, while the proposed ERTSCR has a larger top metal width.

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