Proceedings 18th IEEE VLSI Test Symposium
DOI: 10.1109/vtest.2000.843849
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ESIM: a multimodel design error and fault simulator for logic circuits

Hussain Al-Asaad1,
John P. Hayes
2
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Cited by 6 publications
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Al-Asaad1,
Hayes2
2000
Journal of Electronic Testing
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Al-Asaad1,
Hayes2
2000
Journal of Electronic Testing
7
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New Global Fault Collapsing Techniques for Combinational Library Modules

Al-Asaad
1
2010
International Journal of Modelling and Simulation
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Design verification and functional testing of finite state machines

Weiß
1
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Seth
2
,
Mehta3
et al.
VLSI Design 2001. Fourteenth International Conference on VLSI Design
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