Extreme ultraviolet lithography (EUVL) is a leading next generation lithography technology. Significant progress has been made in developing mask fabrication processes for EUVL. The mask blank for EUVL consists of a low thermal expansion material substrate having a square photomask form factor that is coated with Mo/Si multilayers. SEMI standards are being developed for mask substrates and mounting. Several commercial suppliers are developing polishing processes for LTEM substrates, and they are progressing toward meeting the requirements for flatness, surface roughness, and defects defined in the a draft SEMI standard. One of the challenges in implementing EUVL is to economically fabricate multilayer-coated mask blanks with no printable defects. Significant progress has been made in developing mask blank multilayer coating processes with low added defect density. Besides lowering the added defect density, methods to reduce defect printability, such as defect compensation and buffer layer smoothing, are being developed. Experiments indicate that Mo/Si multilayers that are deposited with ion beam deposition tend to smooth substrate defects, and buffer layer films are being designed to enhance this effect. Targets for buffer layer smoothing are being defined using defect printability simulations. A method for using an electron beam to repair substrate defects after multilayer coating is also being investigated. The mask patterning process for EUVL is nearly the same as that for conventional binary optical lithography masks. EUVL mask patterning efforts are focused on developing the EUV-specific aspects of the patterning process. Eight absorbers have been evaluated against the requirements for EUVL masks, and two absorbers appear most promising. Conventional membrane pellicles are not practical for EUVL, so thermophoretic protection is being developed. Experiments have indicated that thermophoretic protection is effective for >125 nm particles down to at least 50 mTorr pressure. A removable pellicle will be used to protect the mask from defects at all times except during wafer exposure.
