EUVL multilayer mask blank defect mitigation for defect-free EUVL mask fabrication

Abstract

For Extreme Ultra-violet Lithography (EUVL) targeting at 11nm and beyond design rules, the minimum printable EUVL multilayer (ML) mask defect size can be as small as 20-25nm. As a result, the defect-free EUVL ML mask blank fabrication remains the top challenge for EUVL mask. Aspects of this challenge include high quality blank substrate material (low thermal expansion material) fabrication, substrate polishing, substrate cleaning, blank handling, ML deposition, and high sensitivity substrate and blank defect inspection. High investment cost and potential low blank yield due to stringent defect-free requirement can quickly drive up EUVL cost of ownership. It is anticipated, however, the EUVL ML blank yield can be drastically improved if we can allow a few defects on a ML blank. Utilizing such a "defective" grade mask blank to fabricate a defect-free EUVL mask requires several defect mitigation schemes during mask patterning processes. These schemes include modifying mask absorber pattern via repair tool to compensate the effect of an adjacent ML defect and using absorber pattern to cover the ML defects. In this paper, we focused on the study and demonstration of using device pattern to cover limited number of blank defects. The steps of this defect mitigation process include blank fiducial mark patterning, defect location relative to fiducial mark precision measurement, automated pattern shift solution simulation for a given ML defect map, and precision alignment of the device pattern to the blank defects during e-beam write. With these steps, we have successfully demonstrated the coverage of several targeted ML blank defects simultaneously via global device pattern shift.

EUV-CDA: Pattern shift aware critical density analysis for EUV mask layouts

“…Current literature on pattern shift suggest that the total available shift is around 200µm × 200µm [7]. A smaller shift value is chosen to demonstrate our methodology since the runtime of the validation Monte Carlo method becomes too slow with large shift area (≥ 5, 000 hours based on the runtime of [5]).…”

“…The position of the design pattern, which needs to be written on the mask, can be shifted relative to the mask to avoid the defects. Several approaches and results have been shown for such pattern shift based defect avoidance [4]- [7]. A similar, but more general mask floorplanning based defect avoidance has been proposed as well [8], [9].…”

Defect avoidance for EUV photomask readiness at the 7 nm node

“…[16][17][18][22][23][24][25][26][27][28][29][30][31][32] An X and/or Y translation of the full-chip design relative to the blank is essential, however, additional degrees of freedom can also be considered, such as 90-degree rotations, micro-rotations 30 , and mask floorplanning 22,29 . Previous work have shown that microrotations and floorplanning provides only slight improvements for defect avoidance, despite the considerable complexity and resource allocation needed for HVM implementation.…”

Implementable and systematic mitigation of native defects in EUV masks

“…Combining the results obtained in that study with existing methods of mitigating EUV native defects [2,3], we propose a novel method which can identify the location of EUV native defects and then shift the layout pattern to avoid their printing on wafer. In theory, the success rate of defect mitigation depends on pattern density (PD), defect size, defect type and defect location.…”