Evaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGA

Arpinen,; Koskinen,; Salminen,; Hamalainen,; Hannikainen,

doi:10.1109/date.2009.5090665

Cited by 6 publications

(2 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Tools are used to process metadata and automatically generate final executable and configurations. Automation reduces design errors and offers speedup, especially when combined with graphical user interface [7], [9], [10]. III.…”

Section: B Ip Formulation For Reusementioning

confidence: 99%

Applying IP-XACT in product data management

Salminen

Hämäläinen

Hännikäinen

2011

2011 International Symposium on System on Chip (SoC)

View full text Add to dashboard Cite

Key challenge for industrial embedded system companies is product data management (PMD) of rapidly changing requirements, new platforms and own legacy intellectual property. This can be alleviated with IP component reuse methods, platform based design, and Model Driven Development (MDD) methodologies. We propose an open source product integration environment suitable for small and mid-size enterprises (SME) utilizing FPGAs. We extend the use of IP-XACT standard from HW integration at IP-level to board and chip level designs, describe SW as IP-XACT metadata objects, and add reusability status to objects for PDM. We do not modify or extend IP-XACT metadata format to maintain compatibility with standard compliant tools. Instead, we propose naming conventions and usage profiles. An exemplar FPGA-product shows feasibility in practice in our Kactus2 tool. The benefits are covering complete products including SW objects and HW/SW mappings while strictly keeping the standard XML format.

show abstract

Section: B Ip Formulation For Reusementioning

confidence: 99%

Applying IP-XACT in product data management

Salminen

Hämäläinen

Hännikäinen

2011

2011 International Symposium on System on Chip (SoC)

View full text Add to dashboard Cite

show abstract

“…The resulting IP-XACT design flow using UML is also presented which allows automatic RTL component integration based on the proposed transformation rules. Subsequently, the authors further demonstrated their approach in [27], adding modelling concepts, to implement a complex MP-SoC.…”

Section: Hardware Modeling Using Uml and Ip-xactmentioning

confidence: 99%

A high-level methodology for automatically generating dynamic partially reconfigurable systems using IP-XACT and the UML MARTE profile

Ochoa-Ruiz¹,

Labbani²,

Bourennane³

et al. 2012

Des Autom Embed Syst

View full text Add to dashboard Cite

Dynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to increase the flexibility of FPGA designs. However, using DPR for building complex systems remains a daunting task. Recently, approaches based on Model-Driven Engineering (MDE) and UML MARTE standard have emerged which aim to simplify the design of complex SoCs, and in some cases, DPR systems. Nevertheless, many of these approaches lacked a standard intermediate representation to pass from high-levels of descriptions to executable models. However, with the recent standardization of the IP-XACT specification, there is an increasing interest to use it in MDE methodologies to ease system integration and to enable design flow automation. In this paper we propose an MARTE/MDE approach which exploits the capabilities of IP-XACT to model and automatically generate DPR SoC designs. We present the MARTE modeling concepts and how these models are mapped to IP-XACT objects; the emphasis is given to the generation of IP cores that can be used in the Xilinx EDK (Embedded Design Kit) environment, since we aim to develop a complete flow around their Dynamic Partial Reconfiguration design flow. Finally, we present a case study integrating the presented concepts, showing the benefits in design efforts compared with a purely VHDL approach and using solely EDK. Experimental results show a reduction of

show abstract