Evaluation of 3D interconnect routing and stacking strategy to optimize high speed signal transmission for memory on logic

Roullard, J.; Farcy, A.; Capraro, S.; Lacrevaz, T.; Bermond, C.; Houzet, Grégory; Charbonnier, Jean; Fuchs, C.; Ferrandon, C.; Leduc, P.; Fléchet, B.

doi:10.1109/ectc.2012.6248798

Cited by 21 publications

(8 citation statements)

References 12 publications

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“…It turns out that the most chip-to-chip interconnections are smaller than 5 mm and the shielded interconnections are running with 200 MHz. In [3] different stacking strategies, including the side-by-side approach, are compared in terms of density and length and their resulting (theoretical) achievable bandwidth. Differential transmission lines with different concepts for the ground shielding to the substrate are compared with EM simulations in [4].…”

Section: State Of the Artmentioning

confidence: 99%

Characteristics and process stability of complete electrical interconnection structures for a low cost interposer technology

Dittrich

Steinhardt

Heinig

et al. 2015

2015 IEEE 65th Electronic Components and Technology Conference (ECTC)

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Silicon interposers enable the heterogeneous integration of high performance systems. This paper focuses on interconnections from one chip to a neighboring chip in a side-by-side interposer approach. We investigate the performance of interconnections on a typical silicon interposer with polymer applied to the redistribution layer on both sides using electromagnetic simulations. The simulations are valued by measurements. Our measurements show that microstrip lines with <0.3 dB/mm insertion loss at 30 GHz can be achieved with a typical polymer based interposer process. In contrast to other work we extend the microstrip line model with pads on both ends to form a complete interconnection. Our investigations show that an insertion loss of <0.55 dB/mm can be achieved assuming dense inter-connections. We investigate the impact of technological variations during the manufacturing process of a silicon interposer. This is important to ensure electrical functionality (signal and power integrity) of the system in mass production. The results on technology variations during the manufacturing process of an interposer show that variations of 20 % in trace width and trace height are changing the characteristic impedance of the line, but do not significantly affect the signal integrity of sufficiently long lines. In contrast, variations of 20 % in polymer height and polymer permittivity in the redistribution layer have more influence on signal integrity of sufficiently long interposer interconnections

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Section: State Of the Artmentioning

confidence: 99%

Characteristics and process stability of complete electrical interconnection structures for a low cost interposer technology

Dittrich

Steinhardt

Heinig

et al. 2015

2015 IEEE 65th Electronic Components and Technology Conference (ECTC)

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“…In [9] a theoretical circuit analysis showed that a 16 mm-long (RDL) interconnect on silicon interposer has a bandwidth of 535 MHz. However, as shown in the model proposed by [10], this frequency limit can be at least doubled by using a 2 µm width micro-strip line on a silicon interposer with 2 µm-thick bimetal BEOL.…”

Section: Introductionmentioning

confidence: 99%

Investigation of chip-to-chip interconnections for memory-logic communication on 3D interposer technology

Neve

Ryckaert

Plas

et al. 2014

2014 IEEE 18th Workshop on Signal and Power Integrity (SPI)

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A test system for memory-logic communications in silicon interposer is introduced as well as a performance analysis methodology including a fitted model based on eye diagram measurements. First results of the test system with 9 and 18 mmlong interconnects and a 5 channel bus of micro-strip lines with 2-2 and 5-5 µm width and spacing (W-S), targeting Wide-IO communication standard are presented. Measured eye diagrams allow us to compare the performance of the different test systems in combination with a fitted model. All considered systems show operation frequencies higher than 200 MHz for an eye height of at least 35 %. It is demonstrated that the communication system performance is mainly dominated due to weak driver strength (R S > 250 Ω) and secondly by the interconnection dimensions. Design considerations are proposed from the observed results.

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“…It includes technological developments as the Through Silicon Via technology for 3D-WLP and 3D-IC, Cu Pillars and flip chip. It also deals with electromagnetic simulations [5], High Frequency characterization of TSV, Cu-Pillars and Redistribution Layers (RDL), up to 40 GHz [6], and compact modeling [7].…”

Section: Introductionmentioning

confidence: 99%

3D Integration of CMOS image sensor with coprocessor using TSV last and micro-bumps technologies

Coudrain

Henry²,

Berthelot³

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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This paper presents the prototype of a 3D circuit in which a Wafer Level Packaged CMOS image sensor is vertically assembled with an image signal processor in a face-to-back integration scheme. The design flow used to hybrydize the two circuits will be fully described, up to physical implementation. The process technology carried out will be presented in a 200 mm environment. Finally, the 3D assembly will be successfully assessed, concretising the realism of a 3D technology for nomadic imaging systems.

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Evaluation of 3D interconnect routing and stacking strategy to optimize high speed signal transmission for memory on logic

Cited by 21 publications

References 12 publications

Characteristics and process stability of complete electrical interconnection structures for a low cost interposer technology

Characteristics and process stability of complete electrical interconnection structures for a low cost interposer technology

Investigation of chip-to-chip interconnections for memory-logic communication on 3D interposer technology

3D Integration of CMOS image sensor with coprocessor using TSV last and micro-bumps technologies

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