Evidence and solution of over-RESET problem for HfO&lt;inf&gt;X&lt;/inf&gt; based resistive memory with sub-ns switching speed and high endurance

Lee

et al. 2011

Sci. China Inf. Sci.

Resistive random access memory (RRAM or ReRAM) is a non-volatile memory (NVM) technology that consumes minimal energy while offering sub-nanosecond switching. In addition, the data stability against high temperature and cycling wear is very robust, allowing new NVM applications in a variety of markets (automotive, embedded, storage, RAM). Based on sudden conduction through oxide insulators, the characteristics of RRAM technology have still yet to be fully described. In this paper, we present our current understanding of this very promising technology.

Section: Setsupporting

confidence: 72%

Section: Introductionmentioning

confidence: 98%

Resistance switching for RRAM applications

Lee

et al. 2011

Sci. China Inf. Sci.

“…[1][2][3][4][5][6][7] In the past few years, the resistive switching properties have been observed and widely studied in various types of binary metal oxides (BMOs) such as HfO x , [8][9][10][11][12][13] TiO x , 3,4,14-16 TaO x , 17-19 AlO x , 20 NiO x , 21,22 and ZrO x, 23 etc.…”

Section: Introductionmentioning

confidence: 99%

The Role of Ti Buffer Layer Thickness on the Resistive Switching Properties of Hafnium Oxide-Based Resistive Switching Memories

et al. 2017

Ti/HfO-based resistive random access memory (RRAM) has been extensively investigated as an emerging nonvolatile memory (NVM) candidate due to its excellent memory performance and CMOS process compatibility. Although the importance of the role of the Ti buffer layer is well recognized, detailed understanding about the nature of Ti thickness-dependent asymmetric switching is still missing. To realize this, the present work addresses the effects of Ti buffer layer thickness on the switching properties of TiN/Ti/HfO/TiN 1T1R RRAM. Consequently, we have demonstrated a simple strategy to regulate the FORMING voltage, leakage current, memory window, and decrease the operation current, etc. by varying the thickness of the Ti layer on the HfO dielectrics. Accordingly, controllable and reliable bipolar, complementary, and reverse bipolar resistive switching (BRS, CRS, and R-BRS) properties have been demonstrated. This work also provides the direction to avoid unwanted CRS properties during the first RESET operation by decreasing the FORMING voltage. Furthermore, the memory device shows good nonvolatility at ∼1 μA programming current by selecting a proper thickness of Ti buffer layer. To achieve reliable BRS properties for low power application, the operation current has been further optimized, whereas the memory device shows pulse endurance of more than 7 million cycles at a low pulse width of 50 ns and excellent data retention properties of more than 40 h at 150 °C measurement temperature.

2013 IEEE International Test Conference (ITC)

“…Estimations as well as preliminary experimental measurements in their power consumption show considerable improvement over existing technologies [19,2], as maintaining the data stored in memory does not incur any power consumption, and there is no active leakage current (as they are two-terminal passive elements). Reported experimental data show very fast write operations [15], while the speed of a read operation is limited by that of its CMOS sensing circuitry. All these characteristics make memristive memories ideal for integration with computing cores as an extremely dense and low-power on-chip non-volatile memory in the near future [6,34].…”

Section: Introductionmentioning

confidence: 99%

Towards data reliable crossbar-based memristive memories

Ghofrani

Lastras-Montaño

Cheng

2013

A series of breakthroughs in memristive devices have demonstrated the potential of using crossbar-based memristor arrays as ultra-high-density and low-power memory. However, their unique device characteristics could cause data disturbance for both read and write operations resulting in serious data reliability problems.This paper discusses such reliability issues in detail and proposes a comprehensive yet low area-/performance-/energyoverhead solution addressing these problems. The proposed solution applies asymmetric voltages for disturbance confinement, inserts redundancy for disturbance detection, and employs a refreshing mechanism to restore weakened data. The results of a case study show that the average overheads of area, performance and energy consumption for achieving data reliability, over a baseline unreliable memory system, are 3%, 4%, and 19% respectively.