Evidence for suppressed short-channel effects in deep submicron dual-material gate (DMG) partially depleted SOI MOSFETs – A two-dimensional analytical approach

Kumar, M. Jagadesh; Reddy, G. Venkateshwar

doi:10.1016/j.mee.2004.07.058

Cited by 14 publications

(4 citation statements)

References 7 publications

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“…where A 1 , A 2 , B 1 , and B 2 are deduced using the boundary conditions (8)(9)(10)(11)(12) as shown below in (33).…”

Section: Partial Depletion (Gate1) and Near Flatband (Gate2)mentioning

confidence: 99%

“…Instead, the electrostatic performance of the device can be significantly improved by incorporating a step in the surface potential profile using a Dual Material Gate (DMG). The DMG concept has been widely studied to demonstrate the simultaneous suppression of the SCEs and enhancement of trans-conductance, due to the introduction of a step function in the channel surface potential [2][3][4][5][6][7][8][9][10][11]. Recently, improvements in electrical characteristics have been demonstrated by using the DMG structure in planar JLFETs and junctionless nanowire transistors [12,13].…”

Section: Introductionmentioning

confidence: 99%

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A pseudo 2-D surface potential model of a dual material double gate junctionless field effect transistor

2015

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In this paper, we have developed a pseudo twodimensional (2-D) analytical model for the surface potential of a dual-material double-gate junctionless field-effect transistor. We have incorporated the effects of depletion into the source and drain regions to model the surface potential for all three operating modes: (a) full depletion, (b) partial depletion, and (c) near flatband. The effects of the device parameters such as oxide thickness, silicon thickness, and impurity concentration on the surface potential is demonstrated through the model. The model is further extended to derive an expression for the threshold voltage which predicts the expected change with respect to variation in the device parameters. The accuracy of the proposed model is verified against 2-D numerical simulations.

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“…where A 1 , A 2 , B 1 , and B 2 are deduced using the boundary conditions (8)(9)(10)(11)(12) as shown below in (33).…”

Section: Partial Depletion (Gate1) and Near Flatband (Gate2)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A pseudo 2-D surface potential model of a dual material double gate junctionless field effect transistor

2015

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“…The novel attributes of this device are the improved carrier transport efficiency and current driving capability, and reduced DIBL as well as the hot-carrier effect (HCE). 5,6) In this work, we develop a device known as the double-doping polysilicon gate (DDPG) MOSFET, which has advantages similar to those of the DMG MOSFET, and the added benefit of an easier fabrication process. 7,8) Because of a tremendous market demand for low-power applications, current research interests focus on the design of both analog and digital circuits for devices operating in the subthreshold region.…”

Section: Introductionmentioning

confidence: 99%

Two-dimensional semi-analytical model of subthreshold surface potential and drain current for double-doping polysilicon gate MOSFET

Xu¹,

Dai²,

Xu³

et al. 2015

Jpn. J. Appl. Phys.

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A semi-analytical subthreshold surface potential model for double-doping polysilicon gate (DDPG) MOSFETs is presented. By introducing two rectangular sources located in the gate insulator and the channel-depleted region, the two-dimensional (2D) Poisson equations are solved using a semi-analytical method combined with an eigenfunction expansion method. Expressions for the potentials are obtained as special functions of infinite series expressions. A subthreshold drain current is proposed on the basis of the potential profile, and it accounts for the carriers' drift diffusion and thermionic emission theory. The advantage of this work is that the two-dimensional treatment of the gate insulator region has resulted in physical consistency across a dielectric boundary. The proposed model not only offers physical insight into device physics but also provides the basic designing guideline for DDPG MOSFETs, enabling the designer to optimize the device in accordance with the application. Very good agreement for both the subthreshold surface potential and drain current is observed between the model calculations and the simulated results.

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“…Therefore, reduction of hot electron and short cannel effects (SCEs) plays a significant role in downscaling the CMOS technology. Various approaches have been proposed to control these problems [2][3][4][5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%

Nanoscale SOI MOSFETs with electrically induced source/drain extension: Novel attributes and design considerations for suppressed short-channel effects

Orouji

Kumar

2006

Superlattices and Microstructures

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Abstract-Design considerations for a below 100 nm channel length SOI MOSFET with electrically induced shallow source/drain junctions are presented. Our simulation results demonstrate that the application of induced source/drain extensions to the SOI MOSFET will successfully control the SCEs and improve the breakdown voltage even for channel lengths less than 50 nm. We conclude that if the side gate length equals the main gate length, the hot electron effect diminishes optimally.

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Evidence for suppressed short-channel effects in deep submicron dual-material gate (DMG) partially depleted SOI MOSFETs – A two-dimensional analytical approach

Cited by 14 publications

References 7 publications

A pseudo 2-D surface potential model of a dual material double gate junctionless field effect transistor

A pseudo 2-D surface potential model of a dual material double gate junctionless field effect transistor

Two-dimensional semi-analytical model of subthreshold surface potential and drain current for double-doping polysilicon gate MOSFET

Nanoscale SOI MOSFETs with electrically induced source/drain extension: Novel attributes and design considerations for suppressed short-channel effects

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