Experimental 2.0 V power/performance optimization of a 3.6 V-design CMOS microprocessor-PowerPC 601

Bertsch, John E.; Bernstein, K.; Heller, L.G.; Nowak, E.; White, F. R.

doi:10.1109/vlsit.1994.324444

Cited by 5 publications

(2 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To meet the market need, a CMOS-technology scaling technique has been demonstrated at the IBM Microelectronics chip fabrication facility in Essex Junction, Vermont [3]. This approach may allow microprocessor developers to radically reduce the power consumption of a CPU without sacrificing performance, reliability, or yield, or incurring excessive development expense.…”

Section: Introductionmentioning

confidence: 99%

Reduced-voltage power/performance optimization of the 3.6-volt PowerPC 601 Microprocessor

et al. 1995

Self Cite

View full text Add to dashboard Cite

An experimental 2.0*volt low-power PowerPC 601™ Microprocessor built In a modified 3.6-volt, 0.6-tim IBiUI CMOS technology Is described. By using unmodified masks from the 3.6-volt design, a 3x power savings was realized while maintaining nearly the original performance. The use of selective scaling provides high performance at reduced power supply voltage. This technique, applicable to selected existing product designs, may allow early entry into the low-power marlcet while minimizing new process development expense. The technique proposes hyperscaled reductions in specific electrical and physical parameters, while keeping horizontal layout rules unchanged. Static chip designs, which comprise the majority of 601 circuitry, respond well to the alterations. In addition, potential reliability detractors are reduced or eliminated. Challenges to this technique include I/O Interfacing and minimizing leakages associated with low device thresholds. The 601 design and its base technology are described, along with the experimental changes. The paper reviews the motivation behind lowpower microprocessor development, alternative power-saving techniques being practiced, and opportunities for continued power reduction. IntroductionThe use of fully capable microprocessors in portable consumer electronics represents one of the fastest-growing segments of the electronics market. These applications include computing (tablet, laptop, and notebook computers), entertainment (gameboys, virtual reality toys), and communications (cellular phones, wireless modems). By one estimate [1], the subnotebook computer market alone will grow at a 91% compound annual growth rate through 1997, easily exceeding growth rates of the workstation and deskside/desktop segments.

show abstract

Section: Introductionmentioning

confidence: 99%

Reduced-voltage power/performance optimization of the 3.6-volt PowerPC 601 Microprocessor

et al. 1995

Self Cite

View full text Add to dashboard Cite

show abstract

“…A recent experiment demonstrated that a 3.5X power reduction in a high-performance, 0.6pm CMOS product technology, could be achieved with only minor process changes and the same mask set [3]. For the IBM 3.6V PowerPC 1601 microprocessor, an existing, wellcharacterized product was selectively scaled in thresholds and gate oxides.…”

Section: Selective Scalingmentioning

confidence: 99%

Practical performance/power alternatives within an existing CMOS technology generation

Bernstein¹,

Bertsch²,

Clark³

et al.

Proceedings of 1996 International Symposium on Low Power Electronics and Design

Self Cite

View full text Add to dashboard Cite

The tremendous demand for advanced microprocessors is making developers offer a superior product at a competitive price which meets specific performance, power, and reliability requirements. Today's products are designed and built with essentially the same design, fabrication, and test tools used by all industry manufacturers and are constrained by the same device physics, package impedance, heat dissipation capability, and battery energy density limitations. In addition, the current technology generation presents a new set of difficult challenges for the treatment of power dissipation.Lowering voltage to reduce power diminishes FET overdrive and the performance of the device. Recapturing performance by migrating quickly to the next scaled technology generation, however, makes low-power designs expensive, and is not always necessary. Standard full scaling preserves physical and electrical relationships between parameters. On the other hand, selective scaling of specific device parameters may allow the exploitation of existing tools and designs by the use of a different design point on the process "surface." This paper describes recent attempts to explore the feasibility of selective scaling and anticipated constraints associated with future technology generations. SELECTIVE SCALINGConventional CMOS concepts of scaling vertical and horizontal device dimensions and the power supply voltage (Vdd), by a common factor are well documented 111. With the exception of Vdd and threshold voltage (VJ, the principles of MOS scaling have historically been practiced by the industry through several technology generations. Efforts to obtain decreases in Vt with technology scaling, however, have been limited. Subthreshold (leakage) current in MOSFETs is due to weak inversion carriers, whose population density is proportional to the Boltzmann factor, e**-(phi)sub-s/kT, where k, T and @hi)sub-s are Boltzmann's constant, the temperature (absolute) and the silicon surface potential, respectively. Since (phi)sub-s is proportional to (V,-VJ. decreasing Vt leads to exponentially increasing leakage current, thereby limiting the amount of Vt reduction possible. Long-lasting power supply voltage standards, such as the 5V standard, have discouraged the scaling of system-level power supplies. Additionally, high-performance circuit design requirements have limited the allowable reduction in device drive, Vdd-Vt, and will continue to dlo so [2].As an alternative to full scaling, selective scaling exploits existing tool capabilities by finding new device operating poilnts within the process tool window which are acceptable for the application. These alternate process settings allolw operation at reduced voltages, thereby mitigating heat dissipation and battery life issues. Generally, specific device parameters may be identified which require the next generation of process tooling to be improved substantially, and so are ineligible to for selective scaling. These parameters include device length tolerance control, oveirlay/alignment control, imag...

show abstract

A transistor performance figure-of-merit including the effect of gate resistance and its application to scaling to sub-0.25-μm CMOS logic technologies

Chatterjee

Rödder

Chen

1998

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

Experimental 2.0 V power/performance optimization of a 3.6 V-design CMOS microprocessor-PowerPC 601

Cited by 5 publications

References 2 publications

Reduced-voltage power/performance optimization of the 3.6-volt PowerPC 601 Microprocessor

Reduced-voltage power/performance optimization of the 3.6-volt PowerPC 601 Microprocessor

Practical performance/power alternatives within an existing CMOS technology generation

A transistor performance figure-of-merit including the effect of gate resistance and its application to scaling to sub-0.25-μm CMOS logic technologies

Contact Info

Product

Resources

About