A transistor performance figure-of-merit including the effect of gate resistance and its application to scaling to sub-0.25-μm CMOS logic technologies

Chatterjee, Amitava; Rödder, M.; Chen, Ih-Chin

doi:10.1109/16.678526

Cited by 21 publications

(4 citation statements)

References 7 publications

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“…where q: electronic charge, k: Boltzmann's constant, ε: permittivity and E: maximum electric field in the junction [22,23]. The plot gives the linear curve for the Frenkel-Poole and Schottky emission and the slope can be expressed as [21]:…”

Section: Resultsmentioning

confidence: 99%

Temperature dependency and carrier transport mechanisms of Ti/p-type InP Schottky rectifiers

Janardhanam

Lee

Shim

et al. 2010

Journal of Alloys and Compounds

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Section: Resultsmentioning

confidence: 99%

Temperature dependency and carrier transport mechanisms of Ti/p-type InP Schottky rectifiers

Janardhanam

Lee

Shim

et al. 2010

Journal of Alloys and Compounds

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“…2. A small increase of gate delay at 10 m is due to the RC delay by gate resistance, which has become significant in wide transistors [6], [7]. However, there was little reported on the increase of gate delay for narrow channel width transistors.…”

Section: Experiments and Discussionmentioning

confidence: 99%

“…The ring oscillator has also been used to characterize the contribution of various parasitic components to delay time [5]. It is reported that RC delay time induced by gate resistance and capacitance should be considered in evaluating gate delay for wide channel width transistors [6], [7]. However, there has been little study done on the gate delay of narrow channel width transistors.…”

Section: Introductionmentioning

confidence: 99%

Characterization of channel width dependence of gate delay in 0.18-μm CMOS technology

Park

Lee²,

Jang³

1999

IEEE Electron Device Lett.

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The channel width dependence of gate delay in 0.18-m CMOSFET has been characterized. Substantial increase of gate delay observed in the narrow channel width region is found due to channel width independent capacitance components, which is inherent to transistors. An expression for gate delay considering the channel width independent capacitance components and gate sheet resistance is derived and compared with experimental data. The minimum gate delay is shown to result from the compromise between delay components proportional to channel width and proportional to inverse of channel width. Although the channel width independent capacitance is negligible in the wide channel width region, the gate delay of the 1-m channel width ring oscillator increased more than 20% compared with the 5-m channel width ring oscillator.Index Terms-Channel width independent capacitance, gate delay, gate sheet resistance, 0.18-m CMOSFET.

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“…The main purpose is to lower contact resistance. This enhances device performance by reducing parasitic source/drain and gate resistance [1]. At National Semiconductor, 0.35um and larger technology nodes employ Titanium silicide (TiSi) to lower contact resistance.…”

Section: Introductionmentioning

confidence: 99%

Optimized cobalt silicide formation through etch process improvements

2003

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Cobalt silicide is used to reduce contact resistance for sub-micron technology such as 0.25um CMOS. At National Semiconductor, a thin oxide is used to protect areas that are not to be silicided. The selective removal of this oxide to form the silicide mask is critical as it occurs in the highly sensitive cobalt silicide module where neither over nor under etch is acceptable. The final etch uses a low power, CHF 3 /Ar recipe with good across wafer uniformity. In keeping with the advanced process control methodology at National, the etch is end pointed to reduce wafer-to-wafer and etch chamber variability. This paper contains integration aspects of the cobalt silicide module as well as the specifics of the new etch process. The effects of power, pressure and gas flows and details of the end point set up are reviewed, as well as cross section analysis and electrical responses.

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A transistor performance figure-of-merit including the effect of gate resistance and its application to scaling to sub-0.25-μm CMOS logic technologies

Cited by 21 publications

References 7 publications

Temperature dependency and carrier transport mechanisms of Ti/p-type InP Schottky rectifiers

Temperature dependency and carrier transport mechanisms of Ti/p-type InP Schottky rectifiers

Characterization of channel width dependence of gate delay in 0.18-μm CMOS technology

Optimized cobalt silicide formation through etch process improvements

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