Experimental and Analytical Characterization of Dual-Gated Germanium Junctionless p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors

Zhao, Dan; Lee, Choong Hyun; Nishimura, Tomonori; Nagashio, Kosuke; Cheng, Guo An; Toriumi, Akira

doi:10.1143/jjap.51.04da03

Cited by 13 publications

(8 citation statements)

References 31 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As shown in this table, our Ge JNT has much smaller dimensions in both channel length and width, than those from Refs. 6–8. I ON / I OFF current ratio of our device is close to the value in Ref.…”

Section: Characterization Of Ge Jntsupporting

confidence: 89%

“…The subthreshold slope of our devices is about 4.5 times better than best data from Ref. 8 at both high and low V D , which indicates excellent gate control of our devices. The superb gate control can be attributed to the small dimension of our devices and the proper passivation scheme applied before the high‐ k dielectric.…”

Section: Characterization Of Ge Jntsupporting

confidence: 45%

“…In order to compare the planar Ge junctionless transistors 6–8 with our device, a summary of the device characteristics have been listed in Table 1. As shown in this table, our Ge JNT has much smaller dimensions in both channel length and width, than those from Refs.…”

Section: Characterization Of Ge Jntmentioning

confidence: 99%

“…The junctionless nanowire metal–oxide–semiconductor field‐effect transistor (JNT) has recently been demonstrated to be a promising device for sub‐20‐nm nodes 1–5. So far, most devices were made on SOI substrates 1–3, however, approaches of III–V and Ge channels have been initiated for JNT structure 4–8. It is the aim of this Letter to present a functional p‐type Ge JNT with a CMOS‐compatible top–down process.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Junctionless nanowire transistor fabricated with high mobility Ge channel

Yu¹,

Georgiev

Das

et al. 2013

Physica Rapid Research Ltrs

View full text Add to dashboard Cite

The junctionless nanowire metal–oxide–semiconductor field‐effect transistor (JNT) has recently been proposed as an alternative device for sub‐20‐nm nodes. The JNT architecture eliminates the need for forming PN junctions, resulting in simple processing and competitive electrical characteristics. In order to further boost the drive current, alternative channel materials such as III–V and Ge, have been proposed. In this Letter, JNTs with Ge channels have been fabricated by a CMOS‐compatible top–down process. The transistors exhibit the lowest subthreshold slope to date for JNT with Ge channels. The devices with a gate length of 3 μm exhibit a subthreshold slope (SS) of 216 mV/dec with an ION/IOFF current ratio of 1.2 × 103 at VD = –1 V and drain‐induced‐barrier lowering (DIBL) of 87 mV. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

show abstract

Section: Characterization Of Ge Jntsupporting

confidence: 89%

Section: Characterization Of Ge Jntsupporting

confidence: 45%

Section: Characterization Of Ge Jntmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Junctionless nanowire transistor fabricated with high mobility Ge channel

Yu¹,

Georgiev

Das

et al. 2013

Physica Rapid Research Ltrs

View full text Add to dashboard Cite

show abstract

“…6 Ultrathin body (UTB) GOI is a promising substrate for advanced complementary metal-oxide-semiconductor devices, such as junctionless transistors (JLTs). 3,7,8 However, fabricating high-quality UTB GOI substrates directly using the existing methods is difficult, so it is necessary to develop a thinning method to prepare UTB GOI substrates, similar to those used with UTB SOI substrates. 9,10 Wet etching is widely used in the semiconductor industry for wafer cleaning and defect revelation.…”

mentioning

confidence: 99%

Preparation of Ultrathin Germanium on Insulator Films Using a Wet Etching Process

Sun

Liang

Wang

et al. 2015

ECS Solid State Letters

View full text Add to dashboard Cite

We demonstrate a wet etching method to reduce the thickness of thin germanium-on-insulator (GOI) films using a dilute solution (a NH 4 OH:H 2 O 2 :H 2 O 2:1:4000 mixture) at a low temperature (5 • C). The etch rate and thickness uniformity were well controlled. The root mean square roughness after wet etching was less than 0.5 nm and did not degrade compared with the original sample. Finally, back gate junctionless transistors were fabricated using the GOI wafers with 15-nm-thick Ge films, thinned by the developed method. The transistors had good I on /I off ratio and mobility qualities, indicating that the wet etching process effectively thinned the Ge films. © The Author(s) 2015. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 License (CC BY, http://creativecommons.org/licenses/by/4.0/), which permits unrestricted reuse of the work in any medium, provided the original work is properly cited. [DOI: 10.1149/2.0021506ssl] All rights reserved.Manuscript submitted December 30, 2014; revised manuscript received March 16, 2015. Published March 31, 2015 As the feature size of transistors is further reduced to the nanometer scale, Ge is regarded as a promising candidate for use in future transistors because of its high electron and hole mobility compared with Si.1 The combination of the advantages of Ge and on-insulator substrates, such as the reduced junction capacitances and better electrostatic control, has led germanium-on-insulator (GOI) substrates to be considered to have extensive application prospects.2,3 Many methods have been investigated to fabricate GOI, such as Ge condensation techniques, 4 liquid phase epitaxy, 5 and layer transfer techniques. 6 Ultrathin body (UTB) GOI is a promising substrate for advanced complementary metal-oxide-semiconductor devices, such as junctionless transistors (JLTs). 3,7,8 However, fabricating high-quality UTB GOI substrates directly using the existing methods is difficult, so it is necessary to develop a thinning method to prepare UTB GOI substrates, similar to those used with UTB SOI substrates. 9,10Wet etching is widely used in the semiconductor industry for wafer cleaning and defect revelation. 11 In the literature, studies on wet etching bulk Ge are limited, let alone GOI. Ge is not very reactive with single acid and alkali solutions, but it is easily oxidized and its oxide (GeO 2 ) is soluble in aqueous solutions. Therefore, wet etching Ge is usually conducted in a solution containing an oxidizing agent. Brunco et al. 15,16 listed the etch rates of bulk Ge in several different chemicals. However, to prepare UTB GOI substrate, the thickness to remove is often very small, so etch rate need to be well controlled. In addition, owing to the special preparation processes, the etch rate of GOI may not be constant with time and may differ from that of bulk Ge. To obtain ultrathin (less than 15 nm) Ge films, the reported etching methods need to be optimized. Though the feasibility of preparing UTB GOI using we...

show abstract

Fundamentals of Junctionless Field‐Effect Transistors

Sahay¹,

Kumar²

2019

Junctionless Field‐Effect Transistors

View full text Add to dashboard Cite

Experimental and Analytical Characterization of Dual-Gated Germanium Junctionless p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors

Cited by 13 publications

References 31 publications

Junctionless nanowire transistor fabricated with high mobility Ge channel

Junctionless nanowire transistor fabricated with high mobility Ge channel

Preparation of Ultrathin Germanium on Insulator Films Using a Wet Etching Process

Fundamentals of Junctionless Field‐Effect Transistors

Contact Info

Product

Resources

About