Experimental Demonstration of Stacked Gate- All-Around Poly-Si Nanowires Negative Capacitance FETs With Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing Process

Lee, Shen‐Yang; Chen, Hanwei; Shen, Cheng; Kuo, Po-Yi; Chung, Chunhui; Huang, Yen-Fang; Chen, Hsin-Yu; Chao, Tien−Sheng

doi:10.1109/led.2019.2940696

Cited by 28 publications

(23 citation statements)

References 15 publications

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“…In our previous work [23], the device named "NC-FET" is a novel device at that time. However, the NC-effect is still improbable (is it just in the theoretical prediction or can be [24], the author suggested the behavior of non-linear positive capacitance also can induce a body factor less than unity (observe in our previous publication [25]).…”

Section: Introductionmentioning

confidence: 99%

Ultrathin Sub-5-nm Hf₁₋ₓZrₓO₂ for a Stacked Gate-all-Around Nanowire Ferroelectric FET With Internal Metal Gate

Lee

Kuo

et al. 2021

IEEE J. Electron Devices Soc.

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This study investigates a device's ability to boost its on-state current and subthreshold behavior using a ferroelectric field-effect transistor (FeFET) with an ultrathin sub-5-nm Hf₁₋ₓZrₓO₂ (HZO). A conventional field-effect transistor (FET) with pure hafnium (HfO2) is used as a control measure and the impact of an internal metal gate (IMG) is also discussed. The study was conducted by using a sub-5-nm HZO and seed layer to fabricate a gate-all-around (GAA) nanowire (NW); a FeFET with a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure; and a double layer (DL) of the channel. The channel size used in the experiment was approximately 9.6 × 16 nm² and the total thickness of the gate stack was 9.2 nm. This thickness is 50.5% less than our previous experiment. The FeFET exhibits a considerably high Ion-Ioff ratio exceeding 10⁷. The IMG serves as a potential equalizer and the ferroelectric material is arranged in a more symmetrical electric field. This results in a lower subthreshold (sub-VTH) swing (S.S.min = 49.3mV/decade) with a wide range (10³ ) of drain current compared to that without an IMG. The findings indicate that a high-performance GAA FET can be achieved by combining a DL channel, GAA NW, ferroelectric material, and an IMG.

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Section: Introductionmentioning

confidence: 99%

Ultrathin Sub-5-nm Hf₁₋ₓZrₓO₂ for a Stacked Gate-all-Around Nanowire Ferroelectric FET With Internal Metal Gate

Lee

Kuo

et al. 2021

IEEE J. Electron Devices Soc.

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“…ECENTLY, to develop advanced CMOS technology in the sub-3-nm node range, negative capacitance field-effect-transistors (NCFETs) have attracted more attention owing to their exceptional performance and excellent process compatibility with existing CMOS technology [1]- [5]. Actually, nanowire field-effect-transistors with negative capacitance (NC) (NC NWFETs) have been considered the most promising candidates for sub-3-nm node [6]- [7]. Due to the enormous complexity of NC NWFETs, it is quite important to investigate the unconventional effects of NC NWFETs.…”

Section: Introductionmentioning

confidence: 99%

Investigation of Negative DIBL Effect and Miller Effect for Negative Capacitance Nanowire Field-Effect-Transistors

Huang

Zhu

et al. 2020

IEEE J. Electron Devices Soc.

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In this study, the negative DIBL (N-DIBL), negative differential resistance (NDR), and Miller effect of a negative capacitance nanowire filed-effect-transistor (negative capacitance (NC) NWFET) were analyzed by employing the custom-built SPICE model. In the simulation, the minimum subthreshold swing (SS) reduced to 40 mV/decade with negligible hysteresis, and the on-current amplified by approximately three times. The N-DIBL effect was analyzed by building a model, and the results indicated that the N-DIBL is negatively correlated with the SS. Hence, it is indispensable to make trade-offs between the N-DIBL and SS in NC NWFET applications. Moreover, the Miller effect of a NCFET-based inverter was investigated for the first time. The Miller effect of the NC NWFET-based inverter was considerably improved owing to a high on-current and negative internal gate voltage (when external gate voltage is set to 0V), which is beneficial for high-speed circuit building based on NC NWFETs. The overshoot of the NC NWFET-based inverter is ~43.1% less than that of the NWFET-based inverter, and the propagation delay of the NC NWFET-based inverter is ~73.1% less than that of the NWFET-based inverter at ferroelectric thickness TFE=3nm.

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“…These results indicate a new narrow-stripe-confined catalyst formation strategy to obtain uniform indium catalyst droplets, as a key to substantially suppress the SiNW-to-SiNW diameter variation. As a matter of fact, the construction of high-performance SiNW-based logics and sensors [ 31 , 40 ] all demand rather thin, uniform and orderly SiNW arrays as 1D channels to achieve stronger electrostatic modulation control [ 41 ] or higher field-effect sensitivity [ 42 ].…”

Section: Resultsmentioning

confidence: 99%

Nanostripe-Confined Catalyst Formation for Uniform Growth of Ultrathin Silicon Nanowires

et al. 2022

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Uniform growth of ultrathin silicon nanowire (SiNW) channels is the key to accomplishing reliable integration of various SiNW-based electronics, but remains a formidable challenge for catalytic synthesis, largely due to the lack of uniform size control of the leading metallic droplets. In this work, we explored a nanostripe-confined approach to produce highly uniform indium (In) catalyst droplets that enabled the uniform growth of an orderly SiNW array via an in-plane solid–liquid–solid (IPSLS) guided growth directed by simple step edges. It was found that the size dispersion of the In droplets could be reduced substantially from Dcatpl = 20 ± 96 nm on a planar surface to only Dcatns = 88 ± 13 nm when the width of the In nanostripe was narrowed to Wstr= 100 nm, which could be qualitatively explained in a confined diffusion and nucleation model. The improved droplet uniformity was then translated into a more uniform growth of ultrathin SiNWs, with diameter of only Dnw= 28 ± 4 nm, which has not been reported for single-edge guided IPSLS growth. These results lay a solid basis for the construction of advanced SiNW-derived field-effect transistors, sensors and display applications.

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Experimental Demonstration of Stacked Gate- All-Around Poly-Si Nanowires Negative Capacitance FETs With Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing Process

Cited by 28 publications

References 15 publications

Ultrathin Sub-5-nm Hf₁₋ₓZrₓO₂ for a Stacked Gate-all-Around Nanowire Ferroelectric FET With Internal Metal Gate

Ultrathin Sub-5-nm Hf₁₋ₓZrₓO₂ for a Stacked Gate-all-Around Nanowire Ferroelectric FET With Internal Metal Gate

Investigation of Negative DIBL Effect and Miller Effect for Negative Capacitance Nanowire Field-Effect-Transistors

Nanostripe-Confined Catalyst Formation for Uniform Growth of Ultrathin Silicon Nanowires

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