Experimental Testing of the Gigabit IPSec-Compliant Implementations of Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator Board

Chodowiec, Paweł; Gaj, Kris; Bellows, Peter; Schott, Brian

doi:10.1007/3-540-45439-x_15

Cited by 29 publications

(15 citation statements)

References 5 publications

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“…Both academia [3], [8], [9] and industry seem to have focused on the design of Rijndael cores in reconfigurable hardware. These implementations show that contemporary reconfigurable platforms with their rich distributed memory architecture are well suited for Rijndael prototype implementations.…”

Section: Related Workmentioning

confidence: 99%

Design and performance testing of a 2.29-GB/s rijndael processor

Verbauwhede

Schaumont

Kuo

2003

IEEE J. Solid-State Circuits

177

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Abstract-This contribution describes the design and performance testing of an Advanced Encryption Standard (AES) compliant encryption chip that delivers 2.29 GB/s of encryption throughput at 56 mW of power consumption in a 0.18-m CMOS standard cell technology. This integrated circuit implements the Rijndael encryption algorithm, at any combination of block lengths (128, 192, or 25 bits) and key lengths (128, 192, or 256 bits). We present the chip architecture and discuss the design optimizations. We also present measurement results that were obtained from a set of 14 test samples of this chip.

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Section: Related Workmentioning

confidence: 99%

Design and performance testing of a 2.29-GB/s rijndael processor

Verbauwhede

Schaumont

Kuo

2003

IEEE J. Solid-State Circuits

177

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“…They studied mux-modeled s-boxes as well as composite ones. Finally, concerning older technologies 2 , we report in Table 7 an old result of our LUT-based loop architecture and compare it with results of the last AES conference [3,4,5,6]. It is obvious that the methodology applied allowed us to significantly improve previously reported performances of Rijndael implemented in FPGAs.…”

Section: Practical Results and Comparisonsmentioning

confidence: 92%

Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs

Standaert

Rouvroy

Quisquater

et al. 2003

Lecture Notes in Computer Science

116

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Abstract. Performance evaluation of the Advanced Encryption Standard candidates has led to intensive study of both hardware and software implementations. However, although plentiful papers present various implementation results, it seems that efficiency could still be greatly improved by applying good design rules adapted to devices and algorithms. This paper addresses various approaches for efficient FPGA implementations of the Advanced Encryption Standard algorithm. As different applications of the AES algorithm may require different speed/area tradeoffs, we propose a rigorous study of the possible implementation schemes, but also discuss design methodology and algorithmic optimization in order to improve previously reported results. We propose heuristics to evaluate hardware efficiency at different steps of the design process. We also define an optimal pipeline that takes the place and route constraints into account. Resulting circuits significantly improve previously reported results: throughput is up to 18.5 Gbits/sec and area requirements can be limited to 542 slices and 10 RAM blocks with a ratio throughput/area improved by at least 25% of the best-known designs in the Xilinx Virtex-E technology.

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“…The S-Box implementation of the original AES algorithm has been proposed in various works. Most of them either use the table look-up approach [2,6,[8][9][10][11][12] that stores the value of the S-Box in SRAM/ROM, or the arithmetic computing [3][4][5]13,14] that utilizes arithmetic components to perform a SubBytes() transform. The area and speed tradeoff of various S-Box designs have been evaluated in [15].…”

Section: Design Considerationsmentioning

confidence: 99%

A configurable AES processor for enhanced security

Horng

Huang

et al. 2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

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We propose a configurable AES processor for extended-security communication. The proposed architecture can provide up to ¾ ½ different AES block cipher schemes within a reasonable hardware cost. Data can be encrypted not only with secret keys and initial vectors, but also by different block ciphers during the communication. A novel on-the-fly key expansion design is also proposed for 128-, 192-, and 256-bit keys. Our unified hardware can run both the original AES algorithm and the extended AES algorithm. The proposed processor design has been fabricated by a 0.25 m CMOS process, with a silicon area of 6.93mm ¾ -about 200.5K equivalent gates. Under a 66MHz clock, the throughput rate for both the ECB and CBC operation modes are 844.8Mbps, 704Mbps, and 603.4Mbps for 128-bit, 192-bit, and 256-bit keys, respectively.

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Experimental Testing of the Gigabit IPSec-Compliant Implementations of Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator Board

Cited by 29 publications

References 5 publications

Design and performance testing of a 2.29-GB/s rijndael processor

Design and performance testing of a 2.29-GB/s rijndael processor

Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs

A configurable AES processor for enhanced security

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