Experimentally-based analytical model of deep-submicron LDD pMOSFETs in a Bi-MOS hybrid-mode environment

Abstract

The hybrid-mode operation of deep-submicron LDD pMOSFET's has been investigated experimentally. Based on the experimental results, analytical models for the threshold voltage, the device currents, the transconductance, and the output conductance were derived. The various current components in this mode of operation were extracted and identified. The effects of independently biasing the source, drain, gate, and body potentials on the device currents and parameters were examined. The body-

Patterning sub-30-nm MOSFET gate with i-line lithography

“…An HP4156A parameter analyzer was used for device parameter extraction. Interface traps were measured using charge pumping technique [13], [14]. The gate pulses, supplied by an HP8112A pulse generator, have a fixed high level V h and varying base level V b with 50% duty cycle with a frequency of 200 kHz and a 50 ns/V rise/fall gradient.…”

“…The gate pulses, supplied by an HP8112A pulse generator, have a fixed high level V h and varying base level V b with 50% duty cycle with a frequency of 200 kHz and a 50 ns/V rise/fall gradient. During the charge pumping measurement, the trapezoidal pulse is applied to the gate, the substrate is grounded, and the dc charge pumping current is measured from either drain junction or the substrate while the source junction is left floating [13]. This test configuration enables us to eliminate the contribution from the interface traps at the source junction and extract specific signal related to the interface traps for our interests concerning GIDL.…”

A high-speed twin-capacitor BiNMOS (TC-BiNMOS) logic circuit for single battery operation

“…Assuming the circuit operates at a frequency , which corresponds to a period , with a fall time of , and The charging current that flows into is (7) Based on ( 7), the entire operation of charging the node from 0 to 0.9 can be divided into two regions. Region 1: : MP1 operates in saturation mode, since it is a short-channel device, its current can be expressed as [10], [11] (8) where short-channel effect factor; carrier saturation velocity; gate oxide capacitance; channel width of MP1. Substituting ( 8) into (7), the charging time is found to be (9)…”

“…: MP1 now operates in the linear region, and its drain current is given by [10], [11] (10) where effective hole mobility; effective channel length; critical electric field.…”

Temperature-Dependent RF Small-Signal and Noise Characteristics of SOI Dynamic Threshold Voltage MOSFETs

“…D UE TO its larger current driving ability with low leakage current, the dynamic threshold voltage (DT) MOSFET is attractive for low-power applications [1]. Hence, the dc characteristics and modeling of the DT MOSFET have been widely studied since its introduction [2]- [4]. Moreover, the temperature effect on its dc characteristic has also been well investigated [4].…”