2009
DOI: 10.1088/1757-899x/6/1/012014
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Fabrication of polycrystalline silicon nanowires using conventional UV lithography

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Cited by 23 publications
(20 citation statements)
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“…Accurate control of the polysilicon layer Reactive Ion Etching (RIE) rate leads to the formation of nanometric size sidewall spacers that can be used as nanowires. The feasibility of this technological step was previously demonstrated [11].…”
Section: Methodsmentioning
confidence: 93%
“…Accurate control of the polysilicon layer Reactive Ion Etching (RIE) rate leads to the formation of nanometric size sidewall spacers that can be used as nanowires. The feasibility of this technological step was previously demonstrated [11].…”
Section: Methodsmentioning
confidence: 93%
“…The maximum writing field for AURIGIA Compact FIB machine is 197μm 2 ; beyond that area stitching is required, which has a tolerance of ±0.5μm. Also, the minimum spot size that we may get is 30nm with a minimum current of 1pA.…”
Section: Resultsmentioning
confidence: 99%
“…High resolution, which is required for more compact nano-devices, can be somewhat obtained with the expense of depth of focus, hence the device designs involve a tradeoff between short wavelength and large numerical apertures [1][2][3].The limitation of resolution due to diffraction results in searching alternative lithography techniques, which are being developed in research laboratories throughout the world. Moreover, dependency on masks complicates the fabrication as a new mask must be generated for each new design.…”
Section: Introductionmentioning
confidence: 99%
“…The feasibility of these polyscrystalline silicon NWs with curvature radius as low as 50 nm was previously demonstrated [16]. This method allows the fabrication of parallel SiNWs network…”
Section: Then a Polycrystalline Silicon Layer Is Deposited By Low Prmentioning
confidence: 97%