Fabrication of Sub-10-nm Silicon Nanowire Arrays by Size Reduction Lithography

Abstract

A photolithography-based method capable of size reduction to produce sub-10-nm Si nanowire arrays on a wafer scale is described. By conformally depositing a material (silicon oxide or silicon) that has a different etching property over a lithographically defined sacrificial sidewall and selectively removing the sacrificial material, the sidewall material is preserved and can serve as nanopattern mask for further processing. The resolution of this method is not limited by photolithography but by the thickness of the material deposited. The application of size reduction nano-patterning method can range from the fabrication of biosensors to model catalyst systems.

Fabrication of platinum nanoparticles and nanowires by electron beam lithography (EBL) and nanoimprint lithography (NIL): comparison of ethylene hydrogenation kinetics

“…When this size-reduction technique is used multiple times, it can drastically increase feature density. SRL has previously demonstrated the ability to produce a silicon mold with nanowire structures of 7-nm diameter [22,23]. It has also been shown, that a silicon mold can be used in nanoimprint lithography (NIL) to reproduce sub-10 nm features by using the mold to imprint its features into a polymer resist and depositing the desired material into the negative of the mold pattern [24][25][26].…”

Terascale integration via a redesign of the crossbar based on a vertical arrangement of poly-Si nanowires

“…Moreover, silicon is particularly interesting for molecular electronics because it can be terminated with organic moieties carrying wanted electrical properties (like reprogrammable molecules with two well separated conduction states) bonded to the silicon via environmentally robust Si-C bonds [15]. The MSPTs have succeeded in the preparation of silicon wire arrays with pitch p on the 10-nm length scale [16][17][18][19][20][21][22][23][24]: nanowires with width of 7 nm and arrays with p = 35 nm have actually been reported [17,18], whereas the most dense crossbar hitherto produced had a bit density of the order of 10 10 cm −2 [25]. The size to which a nanowire can be scaled down is manifestly limited by the appearance of quantum size effects.…”

NEMS by Sidewall Transfer Lithography

“…It was originally developed for CMOS applications [25], and processes for FinFET fabrication have received increasing attention in recent years with the drive towards strongly submicron channels [26][27][28][29][30][31][32]. STL has also been applied to nanowire arrays in various materials including silicon, diamond, platinum, platinum silicide and nickel silicide, with applications ranging from sensing to catalytic surfaces [33][34][35][36][37][38]. Further applications include field emission electrodes [39,40] and quantum dots [41][42][43].…”