Single nanometre scale quantum dots (QDs) have significant potential for many 'beyond CMOS' nanoelectronics and quantum computation applications. The fabrication and measurement of few nanometre silicon point-contact QD single-electron transistors are reported, which both operate at room temperature (RT) and are fabricated using standard processes. By combining thin silicon-on-insulator wafers, specific device geometry, and controlled oxidation, <10 nm nanoscale point-contact channels are defined. In this limit of the point-contact approach, ultra-small, few nanometre scale QDs are formed, enabling RT measurement of the full QD characteristics, including excited states to be made. A remarkably large QD electron addition energy ∼0.8 eV, and a quantum confinement energy ∼0.3 eV, are observed, implying a QD only ∼1.6 nm in size. In measurements of 19 RT devices, the extracted QD radius lies within a narrow band, from 0.8 to 2.35 nm, emphasising the single-nanometre scale of the QDs. These results demonstrate that with careful control, 'beyond CMOS' RT QD transistors can be produced using current 'conventional' semiconductor device fabrication techniques.

Single-electron devices operating at room temperature require sub-5 nm quantum dots having tunnel junctions of comparable dimensions. Further development in nanoelectronics depends on the capability to generate mesoscopic structures and interfacing these with complementary metal–oxide–semiconductor devices in a single system. The authors employ a combination of two novel methods of fabricating room temperature silicon single-electron transistors (SETs), Fowler–Nordheim scanning probe lithography (F-N SPL) with active cantilevers and cryogenic reactive ion etching followed by pattern-dependent oxidation. The F-N SPL employs a low energy electron exposure of 5–10 nm thick high-resolution molecular resist (Calixarene) resulting in single nanodigit lithographic performance [Rangelow et al., Proc. SPIE 7637, 76370V (2010)]. The followed step of pattern transfer into silicon becomes very challenging because of the extremely low resist thickness, which limits the etching depth. The authors developed a computer simulation code to simulate the reactive ion etching at cryogenic temperatures (−120 °C). In this article, the authors present the alliance of all these technologies used for the manufacturing of SETs capable to operate at room temperatures.

The fabrication of high-performance solid-state silicon quantum-devices requires high resolution patterning with minimal substrate damage. We have fabricated room temperature (RT) singleelectron transistors (SETs) based on point-contact tunnel junctions using a hybrid lithography tool capable of both high resolution thermal scanning probe lithography and high throughput direct laser writing. The best focal z-position and the offset of the tip-and the laser-writing positions were determined in situ with the scanning probe. We demonstrate <100 nm precision in the registration between the high resolution and high throughput lithographies. The SET devices were fabricated on degenerately doped n-type >10 20 /cm 3 silicon on insulator chips using a CMOS compatible geometric oxidation process. The characteristics of the three devices investigated were dominated by the presence of Si nanocrystals or phosphorous atoms embedded within the SiO 2 , forming quantum dots (QDs). The small size and strong localisation of electrons on the QDs facilitated SET operation even at RT. Temperature measurements showed that in the range 300 K>T>∼100 K, the current flow was thermally activated but at <100 K, it was dominated by tunnelling.

-A batch fabrication process for nano-electromechanical systems (NEMS) based on sidewall transfer lithography (STL) is demonstrated. STL is used to form nanoscale flexible silicon suspensions entirely by conventional photolithography. A two-step process for combining microscale and nanoscale features is used to fabricate double-ended and single-ended electrothermal actuators with a minimum feature width of 100 nm and an aspect ratio of 40 : 1. All devices are fabricated by deep reactive ion etching in 4.5 µm thick silicon using bonded silicon-on-insulator material. The process could allow low cost fabrication of nanoscale sensors and actuators.

This paper reports an extension of a recently demonstrated technique to fabricate nano-electromechanical systems (NEMS) using sidewall transfer lithography (STL). The process uses three pattern transfer steps. Each step only requires optical lithography, making the method suitable for low-cost, wafer scale fabrication. The first two involve STL and are used to form nanoscale features such as suspension beams. These may now intersect, breaking an important restriction of single-layer STL NEMS. The third involves conventional lithography and is used to form microscale features such as anchors. Current nanoscale features have a width of 100 nm and an aspect ratio of 50 : 1. The new process should allow mass parallel fabrication of complex NEMS.978-1-4799-7955-4/15/$31.00 ©2015 IEEE