Fast lock scheme for phase-locked loops

Bashir, Amir; Li, Jing; Ivatury, Kiran; Khan, Naveed Ahmad; Gala, Nirav; Familia, Noam; Mohammed, Zulfiqar

doi:10.1109/cicc.2009.5280830

Cited by 16 publications

(3 citation statements)

References 5 publications

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“…PLL lock time takes typically tens of microseconds for a modern digital PLL [8]. Modern processors such as the Nehalem architecture of Intel typically have several micro-seconds lock time [9,1]. A StrongARM 1100 processor measurement result shows that the PLL lock time is insensitive to the difference between the current and target frequencies [10].…”

Section: Clock Frequency Transitionmentioning

confidence: 99%

Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessors

Park

Shin

Chang

et al. 2010

Proceedings of the 16th ACM/IEEE International Symposium on Low Power Electronics and Design

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Dynamic voltage and frequency scaling (DVS) has been studied for well over a decade, and even commercial systems widely support DVS nowadays. Nevertheless, existing DVS transition overhead models do not accurately reflect modern DVS architectures including modern DC-DC converters, PLL (Phase Lock Loop), and voltage and frequency change policies. Incorrect DVS overhead models prevent one from achieving the maximum energy gain, by misleading the DVS control policies. This paper introduces an accurate DVS overhead model, in terms of both energy consumption and time penalty, through detailed observation of modern DVS setups and voltage and frequency change guidelines from vendors. We introduce new major contributors to the DVS overhead including the performance underdrive loss of the DVS-enabled microprocessor, additional inductor IR loss, and so on, as well as consideration of power efficiency from discontinuous-mode DC-DC conversion. Our DVS overhead model enhances the DVS overhead model accuracy from 86% to 238% for Intel Core2 Duo E6850 and LTC3733.

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Section: Clock Frequency Transitionmentioning

confidence: 99%

Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessors

Park

Shin

Chang

et al. 2010

Proceedings of the 16th ACM/IEEE International Symposium on Low Power Electronics and Design

View full text Add to dashboard Cite

show abstract

“…Designs range from conventional PFDs, which measure negative and positive phase offsets on separate binary output signals by producing pulses whose width is the negative/positive phase offset, to more advanced setups [17]. Phase differences are then either forwarded to charge pumps (analog PLLs) [18] or converted to digital counter offsets (digital PLLs). For the latter, an unstable phase difference poses a risk for increased power consumption and likelihood of metastable upsets; see [16], where a filter on phase difference signals for a low-power digital PLL is proposed.…”

Section: Related Work and Comparisonmentioning

confidence: 99%

Synchronizer-Free Digital Link Controller

Bund

Függer

Lenzen

et al. 2020

IEEE Trans. Circuits Syst. I

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This work presents a producer-consumer link between two independent clock domains. The link allows for metastability-free, low-latency, high-throughput communication by slight adjustments to the clock frequencies of the producer and consumer domains steered by a controller circuit. Any such controller cannot deterministically avoid, detect, nor resolve metastability. Typically, this is addressed by synchronizers, incurring a larger dead time in the control loop. We follow the approach of Friedrichs et al. (TC 2018) who proposed metastability-containing circuits. The result is a simple control circuit that may become metastable, yet deterministically avoids buffer underrun or overflow. More specifically, the controller output may become metastable, but this may only affect oscillator speeds within specific bounds. In contrast, communication is guaranteed to remain metastability-free. We formally prove correctness of the producer-consumer link and a possible implementation that has only small overhead. With SPICE simulations of the proposed implementation we further substantiate our claims. The simulation uses 65 nm process running at roughly 2 GHz.

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“…This creative PLL circuit could improve the stability of loop bandwidth by self-compensation, against the variation of manufacturing process parameters, while saving the cost of band gap reference. Based on the self-biased PLL proposed by Reference [1], Patent [2] and Reference [3] have carried on some improvements or adjustments. But the self-biased PLLs mentioned above also suffer from some drawbacks.…”

Section: Introductionmentioning

confidence: 99%

A self-biased PLL with low power and compact area

et al. 2015

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A new low power, low phase jitter, compact realization, and self-biased PLL, which is fabricated on SMIC 40 nm CMOS technology is introduced. The proposed self-biased PLL eliminates extra band gap biasing circuits, and internally generates all the biasing voltages and currents. Meanwhile, all of the PLL dynamic loop parameters, such as loop bandwidth, natural frequency, damping factors are kept constant adaptively. By optimizing the circuit structures, the perfect unity of chip estate, power dissipation, phase jitter, and loop stability is achieved. The PLL consumes 4.2 mW of power under 1.1 V/2.5 V voltage supply at 2.4 GHz VCO frequency, while occupying a die area of less than 0.02 mm 2 (180 110 m 2 /, and the typical period jitter (RMS) is around 2.8 ps.

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Fast lock scheme for phase-locked loops

Cited by 16 publications

References 5 publications

Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessors

Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessors

Synchronizer-Free Digital Link Controller

A self-biased PLL with low power and compact area

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