Fast mixed-mode simulation for accurate MOS bridging fault detection

Chuang, Weitong; Hajj, I.N.

doi:10.1109/iscas.1993.394020

Cited by 8 publications

(2 citation statements)

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“…Moore et al [2000] presented comprehensive delay fault analysis for resistive bridge models and coupling effects, but the delay calculation was not given. Other techniques, such as the mixed-mode simulation method by Chuang and Hajj [1993] and neural network techniques by Shaw et al [2001], give more accurate bridge fault models. But these methods are not efficient for large circuits due to their high time complexity.…”

Section: Introductionmentioning

confidence: 99%

A circuit level fault model for resistive bridges

Lü

Qiu

et al. 2003

ACM Trans. Des. Autom. Electron. Syst.

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Delay faults are an increasingly important test challenge. Modeling bridge faults as delay faults helps delay tests to detect more bridge faults. Traditional bridge fault models are incomplete because these models only model the logic faults or these models are not efficient to use in delay tests for large circuits. In this article, we propose a physically realistic yet economical resistive bridge fault model to model delay faults as well as logic faults. An accurate yet simple delay calculation method is proposed. We also enumerate all possible fault behaviors and present the relationship between input patterns and output behaviors, which is useful in ATPG. Our fault simulation results show the benefit of at-speed tests.

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Section: Introductionmentioning

confidence: 99%

A circuit level fault model for resistive bridges

Lü

Qiu

et al. 2003

ACM Trans. Des. Autom. Electron. Syst.

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“…Renovell [7] [8] presented detailed electrical behaviors for zero bridges and resistive bridges. Other techniques, such as the mixed-mode simulation method by Chuang [9] and neural network techniques by Shaw [10], give more accurate bridge fault models. But these methods are not efficient for large circuits due to their high time complexity.…”

Section: Introductionmentioning

confidence: 99%

A circuit level fault model for resistive opens and bridges

Lü

Qiu

et al.

Proceedings. 21st VLSI Test Symposium, 2003.

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Delay faults are an increasingly important test challenge. Traditional open and bridge fault models are incomplete because only the functional fault or a subset of delay fault are modeled. In this paper, we propose a circuit level model for resistive open and bridge faults. All possible fault behaviors are illustrated and a general resistive bridge delay calculation method is proposed. The new models are practical and easy to use. Fault simulation results show that the new models help the delay test to catch more bridge faults.

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