Fast multiplication in VLSI using wave pipelining techniques

Abstract

Abstract. Wave pipelining is a design methodology that can increase the clock frequency of digital systems. Also known as maximum-rate pipelining, it has long been considered a technique for approaching the physical speed limit of a digital circuit. Unlike conventional pipelining, wave pipelining does not require internal clocked elements to increase throughput. The synchronization of internal computations is achieved by balancing inherent RC delays of combinational logic elements, thus allowing circuits to be pipelined at a very fine-grain level. In this article, we describe the design of a 16 x 16 wave-pipelined multiplier using a 1.0 ~m CMOS process. The multiplier is designed using a conventional static CMOS technology. Simulation results show a speedup of about 7x over a nonpipeline implementation.

Wave-pipelining: a tutorial and research survey

“…1) (4,2) Compressor: Fig. 5(a) shows a manual design of a (4,2) compressor circuit, used as a basic multiplier cell in [24]. Fig.…”

“…Last, due to a lack of commercial tools that are directly applicable to designs using wavepipelining, each group has more or less developed in-house design analysis and optimization tools which enable VLSI design using wave-pipelining. [24]. Circuit level tools were important for this design.…”

A systolic architecture for Kalman-filter-based signal reconstruction using the wave pipeline method

“…To apply the wave pipeline method, some basic building blocks are used to create the basic logic functions INVERTER, NON-INVERTER, OR, AND, NOR, NAND, XOR, and XNOR, with ideally identical propagation delays. Different approaches are available; for example, only 2-input NAND gates and inverters can be used to generate all basic logic functions [4]. Another approach consists of creating of building blocks such as the Normal Process Complementary Pass Transistor Logic (NPCPL) [2].…”