Wave-pipelining: a tutorial and research survey

Burleson, Wayne; Ciesielski, Maciej; Klass, F.; Liu, W.

doi:10.1109/92.711317

Cited by 195 publications

(87 citation statements)

References 30 publications

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“…The premise of wave pipelining is based on the fact that the rate at which logic can propagate through the circuit depends not on the longest path delay but on the difference between the longest and the shortest path delays [18]. One of the main sources of delay variations that limit the application of wave pipelining in CMOS technology is gate-delay datadependence, where gate delay is not independent from the input pattern [18]. This however is not present in some beyond-CMOS technologies (including SWD, QCA, and NML) and the fact that utilizing MIG synthesis results in a circuit comprising one logic primitive (majority gate) increases the applicability of wave pipelining.…”

Section: Introductionmentioning

confidence: 99%

Wave pipelining for majority-based beyond-CMOS technologies

Zografos

Meester

Testa

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

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Abstract-The performance of some emerging nanotechnologies benefits from wave pipelining. The design of such circuits requires new models and algorithms. Thus we show how MajorityInverter Graphs (MIG) can be used for this purpose and we extend the related optimization algorithms. The resulting designs have increased throughput, something that has traditionally been a weak point for the majority of non-charge-based technologies. We benchmark the algorithm on MIG netlists with three different technologies, Spin Wave Devices (SWD), Quantum-dot Cellular Automata (QCA), and NanoMagnetic Logic (NML). We find that the wave pipelined version of the netlists have an improvement in throughput over power of 23×, 13×, and 5× for SWD, QCA, and NML, respectively. In terms of throughput over area ratio, the improvement is 5×, 8×, and 3×, respectively.

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Section: Introductionmentioning

confidence: 99%

Wave pipelining for majority-based beyond-CMOS technologies

Zografos

Meester

Testa

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

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“…The link clock frequency should be sufficiently low to enable reliable data sampling at the receiver, when the latest and earliest data arrival worst cases are considered. We adopt the notation of [23] and draw the delay uncertainty for source-synchronous communication in Fig. 3.…”

Section: Parallel Versus Serial On-chip Communicationmentioning

confidence: 99%

“…These fast links employ wave-pipelining [23]- [25], low-swing differential signaling, fast clock generators and asynchronous protocols. In addition, these links require channel optimization to support wide-bandwidth data transmission over the link wires.…”

Section: Introductionmentioning

confidence: 99%

Asynchronous Current Mode Serial Communication

Dobkin

Moyal

Kolodny

et al. 2010

IEEE Trans. VLSI Syst.

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Abstract-An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the differential level encoded dual-rail (LEDR) two-phase asynchronous protocol, avoiding per-bit handshake and eliminating per-bit synchronization, in contrast with synchronous serial links that rely on complex clock recovery. Novel low-power current signaling driver and receiver circuits are presented, enabling high-speed communication at a very low voltage swing over long wires. In contrast, previous methods employed voltage sensing, resulting in higher swing, higher dynamic power, shorter wires or slower operation. The asynchronous current mode driver is designed to support varying data rates, and it eliminates the need for balanced codes and busy toggling that prevent deep discharge. The data cycle time of the link is equal to a single gate delay, enabling 67 Gb/s throughput in 65-nm technology. Wave-pipelining is employed also by the asynchronous SERDES circuits, to enable such high speed operation. The link was SPICE simulated for 65-nm technology, using wire models obtained by a 3-D EM solver. The link incurs lower power and area relative to synchronous and asynchronous bit-parallel communications, and these relative benefits also scale with technology.

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“…It can also be seen that at any given point of time, multiple waves can be present in the system. In Figure 2-6, there are two waves present in the system at any time instance as indicated by the dotted line [6]. Wave-pipelining techniques increase the design complexity of a system.…”

Section: Wave-pipeliningmentioning

confidence: 99%

A high performance, hybrid wave-pipelined linear feedback shift register with skew tolerant clocks

Nyathi

Delgado-Frias

2003 46th Midwest Symposium on Circuits and Systems

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Chair: Jabulani Nyathi Clock skew and clock distribution are increasingly becoming a major design concern in high performance, high density synchronous systems. Large clock networks are required for efficient clock distribution and they contribute significantly to the power dissipated by the system, while clock skew takes up a considerable percentage of the clock period.Design effort for clock networks is currently estimated to take up 20% of system design time, while power dissipation due to the clock network is reported to be 30% of the total dissipation. It is therefore necessary to investigate the possibilities of other schemes that could results in cost reduction by avoiding complicated architectures while facilitating fast logic.We explore the possibility of managing clock skew and reducing clock loading by applying the hybrid wave-pipelining scheme to a linear feedback shift register. The hybrid wave-pipelining scheme takes advantage of interconnects and data path delays to optimize clock skew and allows the clock to "travel" with its associated data. The system's clock in conjunction with stage delays is used to generate wave-pipelined clocks that have short cycle times and are skew tolerant. The hybrid wave-pipelined clock is designed to mimic the data path elements of the LFSR stage, thus reducing the uncontrolled clock skew, as well as clock loading. Thus, the iv resulting skew is a result of the data path circuitry. A LFSR would provide a good means of measuring clock skew since the common edge of the clock triggers data transfer.Linear feedback shift registers also have numerous common uses including pseudorandom number generator, random pattern generator and analyzer, encryption/decryption and direct sequence spread spectrum for digital signal processing. Their study with different clocking schemes is beneficial as LFSRs are easy to analyze and are found in many applications as mentioned.In this thesis, it is shown that the use of hybrid wave-pipelining provides significant clock skew improvements (six times) compared with a buffered clock design, and also offers improved clock cycle time. There is also potential for a reduction in power dissipation associated with the clock trees, since the scheme reduces the need for complicated clock distribution networks.

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Wave-pipelining: a tutorial and research survey

Cited by 195 publications

References 30 publications

Wave pipelining for majority-based beyond-CMOS technologies

Wave pipelining for majority-based beyond-CMOS technologies

Asynchronous Current Mode Serial Communication

A high performance, hybrid wave-pipelined linear feedback shift register with skew tolerant clocks

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